X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=26a49c10d4fde52fa1bbd42996783a3f7a2cae09;hb=411ad77c05aca0fe83e9cde2f87ab476f8d7d2ff;hp=7888ed3ec7ebd0c45bf8764b52ce5281b5858473;hpb=c34f4a89d16c3001d4687a1281b98b63d9e61715;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index 7888ed3e..26a49c10 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -99,6 +99,12 @@ #define RUNMODE_HALT 0x00 #define RUNMODE_RUN 0x03 +/* Bit patterns when reading from REG_RUN, get run state. */ +#define RUNSTATE_IDLE_BIT (1UL << 0) +#define RUNSTATE_DRAM_BIT (1UL << 1) +#define RUNSTATE_TRGD_BIT (1UL << 2) +#define RUNSTATE_POST_BIT (1UL << 3) + static int ctrl_in(const struct sr_dev_inst *sdi, uint8_t bRequest, uint16_t wValue, uint16_t wIndex, void *data, uint16_t wLength) @@ -108,10 +114,11 @@ static int ctrl_in(const struct sr_dev_inst *sdi, usb = sdi->conn; - if ((ret = libusb_control_transfer(usb->devhdl, - LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, - bRequest, wValue, wIndex, (unsigned char *)data, wLength, - DEFAULT_TIMEOUT_MS)) != wLength) { + ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, + bRequest, wValue, wIndex, data, wLength, + DEFAULT_TIMEOUT_MS); + if (ret != wLength) { sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", wLength, bRequest, wValue, wIndex, libusb_error_name(ret)); @@ -132,10 +139,11 @@ static int ctrl_out(const struct sr_dev_inst *sdi, usb = sdi->conn; - if ((ret = libusb_control_transfer(usb->devhdl, - LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, - bRequest, wValue, wIndex, (unsigned char*)data, wLength, - DEFAULT_TIMEOUT_MS)) != wLength) { + ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, + bRequest, wValue, wIndex, data, wLength, + DEFAULT_TIMEOUT_MS); + if (ret != wLength) { sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", wLength, bRequest, wValue, wIndex, libusb_error_name(ret)); @@ -238,7 +246,8 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); - ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); + ret = sr_resource_open(drvc->sr_ctx, &bitstream, + SR_RESOURCE_FIRMWARE, bitstream_fname); if (ret != SR_OK) { sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); return ret; @@ -247,7 +256,8 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, bitstream_size = (uint32_t)bitstream.size; wrptr = buffer; write_u32le_inc(&wrptr, bitstream_size); - if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { + ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); + if (ret != SR_OK) { sr_err("Cannot initiate FPGA bitstream upload."); sr_resource_close(drvc->sr_ctx, &bitstream); return ret; @@ -260,7 +270,8 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, pos = 0; while (1) { if (pos < bitstream.size) { - len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); + len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, + block, sizeof(block)); if (len < 0) { sr_err("Cannot read FPGA bitstream."); sr_resource_close(drvc->sr_ctx, &bitstream); @@ -304,20 +315,22 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) { int ret; - uint8_t cmd_resp; + uint8_t resp; - if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { + ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); + if (ret != SR_OK) { sr_err("Cannot read response after FPGA bitstream upload."); return ret; } - if (cmd_resp != 0) { + if (resp != 0) { sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", - cmd_resp); + resp); return SR_ERR; } g_usleep(30 * 1000); - if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { + ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); + if (ret != SR_OK) { sr_err("Cannot enable FPGA after bitstream upload."); return ret; } @@ -390,69 +403,77 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) return SR_OK; } -static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) +static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2) { struct dev_context *devc; uint8_t cfg; int ret; devc = sdi->priv; - cfg = 0; - - if (p1) cfg |= 1 << 0; - if (p2) cfg |= 1 << 1; + cfg = 0; + if (p1) + cfg |= 1U << 0; + if (p2) + cfg |= 1U << 1; sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); if (ret != SR_OK) { sr_err("Cannot setup PWM enabled state."); return ret; } + devc->pwm_setting[0].enabled = (p1) ? 1 : 0; devc->pwm_setting[1].enabled = (p2) ? 1 : 0; return SR_OK; } -static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, +static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) { - int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; + static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, }; + struct dev_context *devc; - pwm_setting_dev_t cfg; - pwm_setting_t *setting; + uint8_t ctrl_reg; + struct pwm_setting_dev cfg; + struct pwm_setting *setting; int ret; uint8_t buf[2 * sizeof(uint32_t)]; uint8_t *wrptr; devc = sdi->priv; - if (which < 1 || which > ARRAY_SIZE(CTRL_PWM)) { + if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) { sr_err("Invalid PWM channel: %d.", which); return SR_ERR; } - if (freq > MAX_PWM_FREQ) { + if (freq < 0 || freq > MAX_PWM_FREQ) { sr_err("Too high a PWM frequency: %.1f.", freq); return SR_ERR; } - if (duty > 100 || duty < 0) { + if (duty < 0 || duty > 100) { sr_err("Invalid PWM duty cycle: %f.", duty); return SR_ERR; } + memset(&cfg, 0, sizeof(cfg)); cfg.period = (uint32_t)(PWM_CLOCK / freq); cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); + ctrl_reg = ctrl_reg_tab[which - 1]; wrptr = buf; write_u32le_inc(&wrptr, cfg.period); write_u32le_inc(&wrptr, cfg.duty); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); + ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf); if (ret != SR_OK) { sr_err("Cannot setup PWM%d configuration %d %d.", which, cfg.period, cfg.duty); return ret; } + setting = &devc->pwm_setting[which - 1]; setting->freq = freq; setting->duty = duty; @@ -468,7 +489,6 @@ static int set_defaults(const struct sr_dev_inst *sdi) devc = sdi->priv; devc->capture_ratio = LA2016_DFLT_CAPT_RATIO; - devc->cur_channels = 0xffff; devc->limit_samples = LA2016_DFLT_SAMPLEDEPTH; devc->cur_samplerate = LA2016_DFLT_SAMPLERATE; @@ -476,19 +496,19 @@ static int set_defaults(const struct sr_dev_inst *sdi) if (ret) return ret; - ret = enable_pwm(sdi, 0, 0); + ret = enable_pwm(sdi, FALSE, FALSE); if (ret) return ret; - ret = set_pwm(sdi, 1, SR_KHZ(1), 50); + ret = configure_pwm(sdi, 1, SR_KHZ(1), 50); if (ret) return ret; - ret = set_pwm(sdi, 2, SR_KHZ(100), 50); + ret = configure_pwm(sdi, 2, SR_KHZ(100), 50); if (ret) return ret; - ret = enable_pwm(sdi, 1, 1); + ret = enable_pwm(sdi, TRUE, TRUE); if (ret) return ret; @@ -499,7 +519,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; struct sr_trigger *trigger; - trigger_cfg_t cfg; + struct trigger_cfg cfg; GSList *stages; GSList *channel; struct sr_trigger_stage *stage1; @@ -526,7 +546,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) channel = stage1->matches; while (channel) { match = channel->data; - ch_mask = 1 << match->channel->index; + ch_mask = 1UL << match->channel->index; switch (match->match) { case SR_TRIGGER_ZERO: @@ -566,7 +586,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) "level-triggered 0x%04x, high/falling 0x%04x.", cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); - devc->had_triggers_configured = cfg.enabled != 0; + devc->trigger_involved = cfg.enabled != 0; wrptr = buf; write_u32le_inc(&wrptr, cfg.channels); @@ -592,14 +612,14 @@ static int set_sample_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; double clock_divisor; - uint64_t total; - int ret; - uint16_t divisor; - uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; + uint16_t divider_u16; + uint64_t pre_trigger_samples; + uint64_t pre_trigger_memory; + uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ uint8_t *wrptr; + int ret; devc = sdi->priv; - total = LA2016_PRE_MEM_LIMIT_BASE; if (devc->cur_samplerate > devc->max_samplerate) { sr_err("Too high a sample rate: %" PRIu64 ".", @@ -608,10 +628,10 @@ static int set_sample_config(const struct sr_dev_inst *sdi) } clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; - if (clock_divisor > 0xffff) - clock_divisor = 0xffff; - divisor = (uint16_t)(clock_divisor + 0.5); - devc->cur_samplerate = devc->max_samplerate / divisor; + if (clock_divisor > 65535) + return SR_ERR_ARG; + divider_u16 = (uint16_t)(clock_divisor + 0.5); + devc->cur_samplerate = devc->max_samplerate / divider_u16; if (devc->limit_samples > MAX_SAMPLE_DEPTH) { sr_err("Too high a sample depth: %" PRIu64 ".", @@ -619,21 +639,47 @@ static int set_sample_config(const struct sr_dev_inst *sdi) return SR_ERR; } - devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; + /* + * The acquisition configuration communicates "pre-trigger" + * specs in several formats. sigrok users provide a percentage + * (0-100%), which translates to a pre-trigger samples count + * (assuming that a total samples count limit was specified). + * The device supports hardware compression, which depends on + * slowly changing input data to be effective. Fast changing + * input data may occupy more space in sample memory than its + * uncompressed form would. This is why a third parameter can + * limit the amount of sample memory to use for pre-trigger + * data. Only the upper 24 bits of that memory size spec get + * communicated to the device (written to its FPGA register). + */ + pre_trigger_samples = devc->limit_samples * devc->capture_ratio / 100; + pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE; + pre_trigger_memory *= devc->capture_ratio; + pre_trigger_memory /= 100; - sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples, trigger-pos %" PRIu64 "%%.", - devc->cur_samplerate / 1000, - devc->limit_samples, - devc->capture_ratio); + sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", + devc->cur_samplerate / 1000, devc->limit_samples); + sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", + devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); + /* + * The acquisition configuration occupies a total of 16 bytes: + * - A 34bit total samples count limit (up to 10 billions) that + * is kept in a 40bit register. + * - A 34bit pre-trigger samples count limit (up to 10 billions) + * in another 40bit register. + * - A 32bit pre-trigger memory space limit (in bytes) of which + * the upper 24bits are kept in an FPGA register. + * - A 16bit clock divider which gets applied to the maximum + * samplerate of the device. + * - An 8bit register of unknown meaning. Currently always 0. + */ wrptr = buf; - write_u32le_inc(&wrptr, devc->limit_samples); - write_u8_inc(&wrptr, 0); - write_u32le_inc(&wrptr, devc->pre_trigger_size); - write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xffffff00); - write_u16le_inc(&wrptr, divisor); + write_u40le_inc(&wrptr, devc->limit_samples); + write_u40le_inc(&wrptr, pre_trigger_samples); + write_u24le_inc(&wrptr, pre_trigger_memory >> 8); + write_u16le_inc(&wrptr, divider_u16); write_u8_inc(&wrptr, 0); - ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); if (ret != SR_OK) { sr_err("Cannot setup acquisition configuration."); @@ -653,55 +699,82 @@ static int set_sample_config(const struct sr_dev_inst *sdi) * The meaning of other bit fields is unknown. * * Typical values in order of appearance during execution: + * 0x85e1: idle, no acquisition pending + * IDLE set, TRGD don't care, POST don't care; DRAM don't care + * "In idle state." Takes precedence over all others. * 0x85e2: pre-sampling, samples before the trigger position, * when capture ratio > 0% + * IDLE clear, TRGD clear, POST clear; DRAM don't care + * "Not idle any more, no post yet, not triggered yet." * 0x85ea: pre-sampling complete, now waiting for the trigger * (whilst sampling continuously) + * IDLE clear, TRGD clear, POST set; DRAM don't care + * "Post set thus after pre, not triggered yet" * 0x85ee: trigger seen, capturing post-trigger samples, running + * IDLE clear, TRGD set, POST set; DRAM don't care + * "Triggered and in post, not idle yet." * 0x85ed: idle + * IDLE set, TRGD don't care, POST don't care; DRAM don't care + * "In idle state." TRGD/POST don't care, same meaning as above. */ +static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; +static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; +static const uint16_t runstate_mask_step = + RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; +static const uint16_t runstate_patt_pre_trig = 0; +static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; +static const uint16_t runstate_patt_post_trig = + RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; + static uint16_t run_state(const struct sr_dev_inst *sdi) { - uint16_t state; - static uint16_t previous_state = 0; + static uint16_t previous_state; + int ret; + uint16_t state; + uint8_t buff[sizeof(state)]; + const uint8_t *rdptr; + const char *label; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); + if (ret != SR_OK) { sr_err("Cannot read run state."); return ret; } + rdptr = buff; + state = read_u16le_inc(&rdptr); /* * Avoid flooding the log, only dump values as they change. * The routine is called about every 50ms. */ - if (state != previous_state) { - previous_state = state; - if ((state & 0x0003) == 0x01) { - sr_dbg("Run state: 0x%04x (%s).", state, "idle"); - } else if ((state & 0x000f) == 0x02) { - sr_dbg("Run state: 0x%04x (%s).", state, - "pre-trigger sampling"); - } else if ((state & 0x000f) == 0x0a) { - sr_dbg("Run state: 0x%04x (%s).", state, - "sampling, waiting for trigger"); - } else if ((state & 0x000f) == 0x0e) { - sr_dbg("Run state: 0x%04x (%s).", state, - "post-trigger sampling"); - } else { - sr_dbg("Run state: 0x%04x.", state); - } - } + if (state == previous_state) + return state; + + previous_state = state; + label = NULL; + if ((state & runstate_mask_idle) == runstate_patt_idle) + label = "idle"; + if ((state & runstate_mask_step) == runstate_patt_pre_trig) + label = "pre-trigger sampling"; + if ((state & runstate_mask_step) == runstate_patt_wait_trig) + label = "sampling, waiting for trigger"; + if ((state & runstate_mask_step) == runstate_patt_post_trig) + label = "post-trigger sampling"; + if (label && *label) + sr_dbg("Run state: 0x%04x (%s).", state, label); + else + sr_dbg("Run state: 0x%04x.", state); return state; } -static int la2016_has_triggered(const struct sr_dev_inst *sdi) +static int la2016_is_idle(const struct sr_dev_inst *sdi) { uint16_t state; state = run_state(sdi); - if ((state & 0x3) == 0x1) + if ((state & runstate_mask_idle) == runstate_patt_idle) return 1; return 0; @@ -711,7 +784,8 @@ static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) { int ret; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode))) != SR_OK) { + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); + if (ret != SR_OK) { sr_err("Cannot configure run mode %d.", mode); return ret; } @@ -728,7 +802,8 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc = sdi->priv; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); + if (ret != SR_OK) { sr_err("Cannot read capture info."); return ret; } @@ -738,7 +813,7 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); devc->info.write_pos = read_u32le_inc(&rdptr); - sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d.", + sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", devc->info.n_rep_packets, devc->info.n_rep_packets, devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, @@ -774,7 +849,8 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) return ret; cmd = 0; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); + if (ret != SR_OK) { sr_err("Cannot send command to stop sampling."); return ret; } @@ -828,7 +904,7 @@ SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) return SR_OK; } -static int la2016_start_retrieval(const struct sr_dev_inst *sdi, +static int la2016_start_download(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) { struct dev_context *devc; @@ -842,7 +918,8 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, devc = sdi->priv; usb = sdi->conn; - if ((ret = get_capture_info(sdi)) != SR_OK) + ret = get_capture_info(sdi); + if (ret != SR_OK) return ret; devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; @@ -853,7 +930,8 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", devc->n_transfer_packets_to_read, devc->read_pos); - if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { + ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); + if (ret != SR_OK) { sr_err("Cannot reset USB bulk state."); return ret; } @@ -862,11 +940,13 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, wrptr = wrbuf; write_u32le_inc(&wrptr, devc->read_pos); write_u32le_inc(&wrptr, devc->n_bytes_to_read); - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); + if (ret != SR_OK) { sr_err("Cannot send USB bulk config."); return ret; } - if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { + ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); + if (ret != SR_OK) { sr_err("Cannot unblock USB bulk transfers."); return ret; } @@ -891,10 +971,10 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, devc->transfer = libusb_alloc_transfer(0); libusb_fill_bulk_transfer(devc->transfer, usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, - buffer, to_read, - cb, (void *)sdi, DEFAULT_TIMEOUT_MS); + buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); - if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { + ret = libusb_submit_transfer(devc->transfer); + if (ret != 0) { sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); libusb_free_transfer(devc->transfer); devc->transfer = NULL; @@ -905,67 +985,84 @@ static int la2016_start_retrieval(const struct sr_dev_inst *sdi, return SR_OK; } +/* + * A chunk (received via USB) contains a number of transfers (USB length + * divided by 16) which contain a number of packets (5 per transfer) which + * contain a number of samples (8bit repeat count per 16bit sample data). + */ static void send_chunk(struct sr_dev_inst *sdi, - const uint8_t *packets, unsigned int num_tfers) + const uint8_t *packets, size_t num_xfers) { struct dev_context *devc; struct sr_datafeed_logic logic; struct sr_datafeed_packet sr_packet; unsigned int max_samples, n_samples, total_samples, free_n_samples; - unsigned int i, j, k; - int do_signal_trigger; - uint16_t *wp; + size_t num_pkts; + gboolean do_signal_trigger; + uint8_t *wp; const uint8_t *rp; - uint16_t state; - uint8_t repetitions; + uint16_t sample_value; + size_t repetitions; + uint8_t sample_buff[sizeof(sample_value)]; devc = sdi->priv; - logic.unitsize = 2; + logic.unitsize = sizeof(sample_buff); logic.data = devc->convbuffer; sr_packet.type = SR_DF_LOGIC; sr_packet.payload = &logic; - max_samples = devc->convbuffer_size / 2; + max_samples = devc->convbuffer_size / sizeof(sample_buff); n_samples = 0; - wp = (uint16_t *)devc->convbuffer; + wp = devc->convbuffer; total_samples = 0; - do_signal_trigger = 0; + do_signal_trigger = FALSE; - if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { + if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { std_session_send_df_trigger(sdi); - devc->reading_behind_trigger = 1; + devc->trigger_marked = TRUE; } rp = packets; - for (i = 0; i < num_tfers; i++) { - for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { + while (num_xfers--) { + num_pkts = NUM_PACKETS_IN_CHUNK; + while (num_pkts--) { + /* + * Flush the conversion buffer when a trigger + * location needs to get communicated, or when + * an to-get-expected sample repetition count + * would no longer fit into the buffer. + */ free_n_samples = max_samples - n_samples; if (free_n_samples < 256 || do_signal_trigger) { - logic.length = n_samples * 2; + logic.length = n_samples * sizeof(sample_buff);; sr_session_send(sdi, &sr_packet); n_samples = 0; - wp = (uint16_t *)devc->convbuffer; + wp = devc->convbuffer; if (do_signal_trigger) { std_session_send_df_trigger(sdi); - do_signal_trigger = 0; + do_signal_trigger = FALSE; } } - state = read_u16le_inc(&rp); + sample_value = read_u16le_inc(&rp); repetitions = read_u8_inc(&rp); - for (j = 0; j < repetitions; j++) - *wp++ = state; n_samples += repetitions; total_samples += repetitions; devc->total_samples += repetitions; - if (!devc->reading_behind_trigger) { - devc->n_reps_until_trigger--; - if (devc->n_reps_until_trigger == 0) { - devc->reading_behind_trigger = 1; - do_signal_trigger = 1; + + write_u16le(sample_buff, sample_value); + while (repetitions--) { + memcpy(wp, sample_buff, logic.unitsize); + wp += logic.unitsize; + } + + if (devc->trigger_involved && !devc->trigger_marked) { + if (!--devc->n_reps_until_trigger) { + devc->trigger_marked = TRUE; + do_signal_trigger = TRUE; sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", devc->total_samples, (double)devc->total_samples / devc->cur_samplerate * 1e3); @@ -975,7 +1072,7 @@ static void send_chunk(struct sr_dev_inst *sdi, (void)read_u8_inc(&rp); /* Skip sequence number. */ } if (n_samples) { - logic.length = n_samples * 2; + logic.length = n_samples * logic.unitsize; sr_session_send(sdi, &sr_packet); if (do_signal_trigger) { std_session_send_df_trigger(sdi); @@ -1000,7 +1097,7 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { sr_err("USB bulk transfer timeout."); - devc->transfer_finished = 1; + devc->download_finished = TRUE; } send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); @@ -1021,7 +1118,8 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) transfer->buffer, to_read, receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); - if ((ret = libusb_submit_transfer(transfer)) == 0) + ret = libusb_submit_transfer(transfer); + if (ret == 0) return; sr_err("Cannot submit another USB transfer: %s.", libusb_error_name(ret)); @@ -1029,7 +1127,7 @@ static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) g_free(transfer->buffer); libusb_free_transfer(transfer); - devc->transfer_finished = 1; + devc->download_finished = TRUE; } SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) @@ -1046,17 +1144,17 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) devc = sdi->priv; drvc = sdi->driver->context; - if (devc->have_trigger == 0) { - if (la2016_has_triggered(sdi) == 0) { + if (!devc->completion_seen) { + if (!la2016_is_idle(sdi)) { /* Not yet ready for sample data download. */ return TRUE; } - devc->have_trigger = 1; - devc->transfer_finished = 0; - devc->reading_behind_trigger = 0; + devc->completion_seen = TRUE; + devc->download_finished = FALSE; + devc->trigger_marked = FALSE; devc->total_samples = 0; /* We can start downloading sample data. */ - if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { + if (la2016_start_download(sdi, receive_transfer) != SR_OK) { sr_err("Cannot start acquisition data download."); return FALSE; } @@ -1069,7 +1167,7 @@ SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) tv.tv_sec = tv.tv_usec = 0; libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); - if (devc->transfer_finished) { + if (devc->download_finished) { sr_dbg("Download finished, post processing."); std_session_send_df_frame_end(sdi); @@ -1094,7 +1192,9 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) struct dev_context *devc; uint16_t state; uint8_t buf[8]; - int16_t purchase_date_bcd[2]; + const uint8_t *rdptr; + uint8_t date_yy, date_mm; + uint8_t dinv_yy, dinv_mm; uint8_t magic; const char *bitstream_fn; int ret; @@ -1102,20 +1202,24 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) devc = sdi->priv; /* - * Four EEPROM bytes at offset 0x20 are purchase year and month - * in BCD format, with 16bit complemented checksum. For example - * 20 04 df fb translates to 2020-04. This can help identify the - * age of devices when unknown magic numbers are seen. + * Four EEPROM bytes at offset 0x20 are the manufacturing date, + * year and month in BCD format, followed by inverted values for + * consistency checks. For example bytes 20 04 df fb translate + * to 2020-04. This information can help identify the vintage of + * devices when unknown magic numbers are seen. */ - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { - sr_err("Cannot read purchase date in EEPROM."); + ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t)); + if (ret != SR_OK) { + sr_err("Cannot read manufacture date in EEPROM."); } else { - sr_dbg("Purchase date: 20%02hx-%02hx.", - (purchase_date_bcd[0]) & 0xff, - (purchase_date_bcd[0] >> 8) & 0xff); - if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { - sr_err("Purchase date fails checksum test."); - } + rdptr = &buf[0]; + date_yy = read_u8_inc(&rdptr); + date_mm = read_u8_inc(&rdptr); + dinv_yy = read_u8_inc(&rdptr); + dinv_mm = read_u8_inc(&rdptr); + sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); + if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) + sr_warn("Manufacture date fails checksum test."); } /* @@ -1160,17 +1264,18 @@ SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) sr_err("Cannot read EEPROM device identifier bytes."); return ret; } - - magic = 0; - if (buf[0] == (0xff & ~buf[1])) { + if ((buf[0] ^ buf[1]) == 0xff) { /* Primary copy of magic passes complement check. */ + sr_dbg("Using primary copy of device type magic number."); magic = buf[0]; - } else if (buf[4] == (0xff & ~buf[5])) { + } else if ((buf[4] ^ buf[5]) == 0xff) { /* Backup copy of magic passes complement check. */ sr_dbg("Using backup copy of device type magic number."); magic = buf[4]; + } else { + sr_err("Cannot find consistent device type identification."); + magic = 0; } - sr_dbg("Device type: magic number is %hhu.", magic); /* Select the FPGA bitstream depending on the model. */