X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fkingst-la2016%2Fprotocol.c;h=26a49c10d4fde52fa1bbd42996783a3f7a2cae09;hb=411ad77c05aca0fe83e9cde2f87ab476f8d7d2ff;hp=1058a345fb2e4536d5d5b40bf0c739eef4834da9;hpb=8b172e78f6b9643cd62384df87459acb71f60d62;p=libsigrok.git diff --git a/src/hardware/kingst-la2016/protocol.c b/src/hardware/kingst-la2016/protocol.c index 1058a345..26a49c10 100644 --- a/src/hardware/kingst-la2016/protocol.c +++ b/src/hardware/kingst-la2016/protocol.c @@ -21,15 +21,10 @@ */ #include -#include -#include -#include -#include -#include -#include -#include -#include + #include +#include + #include "libsigrok-internal.h" #include "protocol.h" @@ -39,56 +34,96 @@ #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" +/* Maximum device capabilities. May differ between models. */ #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) -#define MAX_SAMPLE_DEPTH 10e9 -#define MAX_PWM_FREQ SR_MHZ(20) -#define PWM_CLOCK SR_MHZ(200) /* this is 200MHz for both the LA2016 and LA1016 */ - -/* usb vendor class control requests to the cypress FX2 microcontroller */ -#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ -#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ -#define CMD_FPGA_ENABLE 0x10 -#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ -#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ -#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ +#define MAX_SAMPLE_DEPTH 10e9 +#define MAX_PWM_FREQ SR_MHZ(20) +#define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ /* - * fpga spi register addresses for control request CMD_FPGA_SPI: - * There are around 60 byte-wide registers within the fpga and - * these are the base addresses used for accessing them. - * On the spi bus, the msb of the address byte is set for read - * and cleared for write, but that is handled by the fx2 mcu - * as appropriate. In this driver code just use IN transactions - * to read, OUT to write. + * Default device configuration. Must be applicable to any of the + * supported devices (no model specific default values yet). Specific + * firmware implementation details unfortunately won't let us detect + * and keep using previously configured values. */ -#define REG_RUN 0x00 /* read capture status, write capture start */ -#define REG_PWM_EN 0x02 /* user pwm channels on/off */ -#define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ -#define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ -#define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ -#define REG_TRIGGER 0x20 /* write level and edge trigger config */ -#define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ -#define REG_PWM1 0x70 /* write config for user pwm1 */ -#define REG_PWM2 0x78 /* write config for user pwm2 */ +#define LA2016_DFLT_SAMPLERATE SR_MHZ(100) +#define LA2016_DFLT_SAMPLEDEPTH (5 * 1000 * 1000) +#define LA2016_DFLT_CAPT_RATIO 5 /* Capture ratio, in percent. */ + +/* TODO + * What is the origin and motivation of that 128Mi literal? What is its + * unit? How does it relate to a device's hardware capabilities? How to + * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value? + * It cannot be sample count. Is it memory size in bytes perhaps? + */ +#define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024) + +/* USB vendor class control requests, executed by the Cypress FX2 MCU. */ +#define CMD_FPGA_ENABLE 0x10 +#define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ +#define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ +#define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ +#define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ +#define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ +#define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ + +/* + * FPGA register addresses (base addresses when registers span multiple + * bytes, in that case data is kept in little endian format). Passed to + * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail + * of SPI transfers encoding the read (1) or write (0) direction in the + * MSB of the address field. There are some 60 byte-wide FPGA registers. + * + * Unfortunately the FPGA registers change their meaning between the + * read and write directions of access, or exclusively provide one of + * these directions and not the other. This is an arbitrary vendor's + * choice, there is nothing which the sigrok driver could do about it. + * Values written to registers typically cannot get read back, neither + * verified after writing a configuration, nor queried upon startup for + * automatic detection of the current configuration. Neither appear to + * be there echo registers for presence and communication checks, nor + * version identifying registers, as far as we know. + */ +#define REG_RUN 0x00 /* Read capture status, write start capture. */ +#define REG_PWM_EN 0x02 /* User PWM channels on/off. */ +#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ +#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ +#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ +#define REG_TRIGGER 0x20 /* write level and edge trigger config. */ +#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ +#define REG_PWM1 0x70 /* Write config for user PWM1. */ +#define REG_PWM2 0x78 /* Write config for user PWM2. */ + +/* Bit patterns to write to REG_RUN, setup run mode. */ +#define RUNMODE_HALT 0x00 +#define RUNMODE_RUN 0x03 + +/* Bit patterns when reading from REG_RUN, get run state. */ +#define RUNSTATE_IDLE_BIT (1UL << 0) +#define RUNSTATE_DRAM_BIT (1UL << 1) +#define RUNSTATE_TRGD_BIT (1UL << 2) +#define RUNSTATE_POST_BIT (1UL << 3) static int ctrl_in(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; usb = sdi->conn; - if ((ret = libusb_control_transfer( - usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, - bRequest, wValue, wIndex, (unsigned char *)data, wLength, - DEFAULT_TIMEOUT_MS)) != wLength) { - sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.", - wLength, bRequest, wValue, wIndex, - libusb_error_name(ret)); + ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, + bRequest, wValue, wIndex, data, wLength, + DEFAULT_TIMEOUT_MS); + if (ret != wLength) { + sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", + wLength, bRequest, wValue, wIndex, + libusb_error_name(ret)); + sr_err("Cannot read %d bytes from USB: %s.", + wLength, libusb_error_name(ret)); return SR_ERR; } @@ -96,74 +131,154 @@ static int ctrl_in(const struct sr_dev_inst *sdi, } static int ctrl_out(const struct sr_dev_inst *sdi, - uint8_t bRequest, uint16_t wValue, uint16_t wIndex, - void *data, uint16_t wLength) + uint8_t bRequest, uint16_t wValue, uint16_t wIndex, + void *data, uint16_t wLength) { struct sr_usb_dev_inst *usb; int ret; usb = sdi->conn; - if ((ret = libusb_control_transfer( - usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, - bRequest, wValue, wIndex, (unsigned char*)data, wLength, - DEFAULT_TIMEOUT_MS)) != wLength) { - sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.", - wLength, bRequest, wValue, wIndex, - libusb_error_name(ret)); + ret = libusb_control_transfer(usb->devhdl, + LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, + bRequest, wValue, wIndex, data, wLength, + DEFAULT_TIMEOUT_MS); + if (ret != wLength) { + sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", + wLength, bRequest, wValue, wIndex, + libusb_error_name(ret)); + sr_err("Cannot write %d bytes to USB: %s.", + wLength, libusb_error_name(ret)); return SR_ERR; } return SR_OK; } -static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) +/* + * Check the necessity for FPGA bitstream upload, because another upload + * would take some 600ms which is undesirable after program startup. Try + * to access some FPGA registers and check the values' plausibility. The + * check should fail on the safe side, request another upload when in + * doubt. A positive response (the request to continue operation with the + * currently active bitstream) should be conservative. Accessing multiple + * registers is considered cheap compared to the cost of bitstream upload. + * + * It helps though that both the vendor software and the sigrok driver + * use the same bundle of MCU firmware and FPGA bitstream for any of the + * supported models. We don't expect to successfully communicate to the + * device yet disagree on its protocol. Ideally we would access version + * identifying registers for improved robustness, but are not aware of + * any. A bitstream reload can always be forced by a power cycle. + */ +static int check_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + uint8_t init_rsp; + int ret; + uint16_t run_state; + uint8_t pwm_en; + size_t read_len; + uint8_t buff[sizeof(run_state)]; + const uint8_t *rdptr; + + sr_dbg("Checking operation of the FPGA bitstream."); + + init_rsp = ~0; + ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); + if (ret != SR_OK || init_rsp != 0) { + sr_dbg("FPGA init query failed, or unexpected response."); + return SR_ERR_IO; + } + + read_len = sizeof(run_state); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (run state)."); + return SR_ERR_IO; + } + rdptr = buff; + run_state = read_u16le_inc(&rdptr); + sr_spew("FPGA register: run state 0x%04x.", run_state); + if (run_state && (run_state & 0x3) != 0x1) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + if (run_state && (run_state & ~0xf) != 0x85e0) { + sr_dbg("Unexpected FPGA register content (run state)."); + return SR_ERR_DATA; + } + + read_len = sizeof(pwm_en); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); + if (ret != SR_OK) { + sr_dbg("FPGA register access failed (PWM enable)."); + return SR_ERR_IO; + } + rdptr = buff; + pwm_en = read_u8_inc(&rdptr); + sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); + if ((pwm_en & 0x3) != 0x0) { + sr_dbg("Unexpected FPGA register content (PWM enable)."); + return SR_ERR_DATA; + } + + sr_info("Could re-use current FPGA bitstream. No upload required."); + return SR_OK; +} + +static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, + const char *bitstream_fname) { - struct dev_context *devc; struct drv_context *drvc; struct sr_usb_dev_inst *usb; struct sr_resource bitstream; + uint32_t bitstream_size; uint8_t buffer[sizeof(uint32_t)]; uint8_t *wrptr; - uint8_t cmd_resp; uint8_t block[4096]; int len, act_len; unsigned int pos; int ret; - unsigned int zero_pad_to = 0x2c000; + unsigned int zero_pad_to; - devc = sdi->priv; drvc = sdi->driver->context; usb = sdi->conn; sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); - ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); + ret = sr_resource_open(drvc->sr_ctx, &bitstream, + SR_RESOURCE_FIRMWARE, bitstream_fname); if (ret != SR_OK) { - sr_err("could not find fpga firmware %s!", bitstream_fname); + sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); return ret; } - devc->bitstream_size = (uint32_t)bitstream.size; + bitstream_size = (uint32_t)bitstream.size; wrptr = buffer; - write_u32le_inc(&wrptr, devc->bitstream_size); - if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { - sr_err("failed to give upload init command"); + write_u32le_inc(&wrptr, bitstream_size); + ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); + if (ret != SR_OK) { + sr_err("Cannot initiate FPGA bitstream upload."); sr_resource_close(drvc->sr_ctx, &bitstream); return ret; } + zero_pad_to = bitstream_size; + zero_pad_to += LA2016_EP2_PADDING - 1; + zero_pad_to /= LA2016_EP2_PADDING; + zero_pad_to *= LA2016_EP2_PADDING; pos = 0; while (1) { if (pos < bitstream.size) { - len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); + len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, + block, sizeof(block)); if (len < 0) { - sr_err("failed to read from fpga bitstream!"); + sr_err("Cannot read FPGA bitstream."); sr_resource_close(drvc->sr_ctx, &bitstream); return SR_ERR; } } else { - // fill with zero's until zero_pad_to + /* Zero-pad until 'zero_pad_to'. */ len = zero_pad_to - pos; if ((unsigned)len > sizeof(block)) len = sizeof(block); @@ -172,14 +287,17 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits if (len == 0) break; - ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); + ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, + &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); if (ret != 0) { - sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret)); + sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", + pos, (int)len, libusb_error_name(ret)); ret = SR_ERR; break; } if (act_len != len) { - sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len); + sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", + pos, (int)len, act_len); ret = SR_ERR; break; } @@ -188,25 +306,36 @@ static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bits sr_resource_close(drvc->sr_ctx, &bitstream); if (ret != 0) return ret; - sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size); + sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", + bitstream.size); + + return SR_OK; +} + +static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) +{ + int ret; + uint8_t resp; - if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { - sr_err("failed to read response after FPGA bitstream upload"); + ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); + if (ret != SR_OK) { + sr_err("Cannot read response after FPGA bitstream upload."); return ret; } - if (cmd_resp != 0) { - sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp); + if (resp != 0) { + sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", + resp); return SR_ERR; } + g_usleep(30 * 1000); - g_usleep(30000); - - if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { - sr_err("failed enable fpga"); + ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); + if (ret != SR_OK) { + sr_err("Cannot enable FPGA after bitstream upload."); return ret; } + g_usleep(40 * 1000); - g_usleep(40000); return SR_OK; } @@ -217,56 +346,48 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) devc = sdi->priv; - uint16_t duty_R79,duty_R56; + uint16_t duty_R79, duty_R56; uint8_t buf[2 * sizeof(uint16_t)]; uint8_t *wrptr; - /* clamp threshold setting within valid range for LA2016 */ + /* Clamp threshold setting to valid range for LA2016. */ if (voltage > 4.0) { voltage = 4.0; - } - else if (voltage < -4.0) { + } else if (voltage < -4.0) { voltage = -4.0; } /* - * The fpga has two programmable pwm outputs which feed a dac that - * is used to adjust input offset. The dac changes the input - * swing around the fixed fpga input threshold. - * The two pwm outputs can be seen on R79 and R56 respectvely. - * Frequency is fixed at 100kHz and duty is varied. - * The R79 pwm uses just three settings. - * The R56 pwm varies with required threshold and its behaviour - * also changes depending on the setting of R79 PWM. - */ - - /* - * calculate required pwm duty register values from requested threshold voltage - * see last page of schematic (on wiki) for an explanation of these numbers + * Two PWM output channels feed one DAC which generates a bias + * voltage, which offsets the input probe's voltage level, and + * in combination with the FPGA pins' fixed threshold result in + * a programmable input threshold from the user's perspective. + * The PWM outputs can be seen on R79 and R56 respectively, the + * frequency is 100kHz and the duty cycle varies. The R79 PWM + * uses three discrete settings. The R56 PWM varies with desired + * thresholds and depends on the R79 PWM configuration. See the + * schematics comments which discuss the formulae. */ if (voltage >= 2.9) { - duty_R79 = 0; /* this pwm is off (0V)*/ + duty_R79 = 0; /* PWM off (0V). */ duty_R56 = (uint16_t)(302 * voltage - 363); - } - else if (voltage <= -0.4) { - duty_R79 = 0x02D7; /* 72% duty */ - duty_R56 = (uint16_t)(302 * voltage + 1090); - } - else { - duty_R79 = 0x00f2; /* 25% duty */ + } else if (voltage > -0.4) { + duty_R79 = 0x00f2; /* 25% duty cycle. */ duty_R56 = (uint16_t)(302 * voltage + 121); + } else { + duty_R79 = 0x02d7; /* 72% duty cycle. */ + duty_R56 = (uint16_t)(302 * voltage + 1090); } - /* clamp duty register values at sensible limits */ + /* Clamp duty register values to sensible limits. */ if (duty_R56 < 10) { duty_R56 = 10; - } - else if (duty_R56 > 1100) { + } else if (duty_R56 > 1100) { duty_R56 = 1100; } - sr_dbg("set threshold voltage %.2fV", voltage); - sr_dbg("duty_R56=0x%04x, duty_R79=0x%04x", duty_R56, duty_R79); + sr_dbg("Set threshold voltage %.2fV.", voltage); + sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); wrptr = buf; write_u16le_inc(&wrptr, duty_R56); @@ -274,7 +395,7 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting new threshold voltage of %.2fV", voltage); + sr_err("Cannot set threshold voltage %.2fV.", voltage); return ret; } devc->threshold_voltage = voltage; @@ -282,67 +403,77 @@ static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) return SR_OK; } -static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) +static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2) { struct dev_context *devc; uint8_t cfg; int ret; devc = sdi->priv; - cfg = 0; - if (p1) cfg |= 1 << 0; - if (p2) cfg |= 1 << 1; + cfg = 0; + if (p1) + cfg |= 1U << 0; + if (p2) + cfg |= 1U << 1; + sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); - sr_dbg("set pwm enable %d %d", p1, p2); ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); if (ret != SR_OK) { - sr_err("error setting new pwm enable 0x%02x", cfg); + sr_err("Cannot setup PWM enabled state."); return ret; } + devc->pwm_setting[0].enabled = (p1) ? 1 : 0; devc->pwm_setting[1].enabled = (p2) ? 1 : 0; return SR_OK; } -static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) +static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which, + float freq, float duty) { - int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; + static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, }; + struct dev_context *devc; - pwm_setting_dev_t cfg; - pwm_setting_t *setting; + uint8_t ctrl_reg; + struct pwm_setting_dev cfg; + struct pwm_setting *setting; int ret; uint8_t buf[2 * sizeof(uint32_t)]; uint8_t *wrptr; devc = sdi->priv; - if (which < 1 || which > 2) { - sr_err("invalid pwm channel: %d", which); + if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) { + sr_err("Invalid PWM channel: %d.", which); return SR_ERR; } - if (freq > MAX_PWM_FREQ) { - sr_err("pwm frequency too high: %.1f", freq); + if (freq < 0 || freq > MAX_PWM_FREQ) { + sr_err("Too high a PWM frequency: %.1f.", freq); return SR_ERR; } - if (duty > 100 || duty < 0) { - sr_err("invalid pwm percentage: %f", duty); + if (duty < 0 || duty > 100) { + sr_err("Invalid PWM duty cycle: %f.", duty); return SR_ERR; } + memset(&cfg, 0, sizeof(cfg)); cfg.period = (uint32_t)(PWM_CLOCK / freq); cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); - sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty); + sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); + ctrl_reg = ctrl_reg_tab[which - 1]; wrptr = buf; write_u32le_inc(&wrptr, cfg.period); write_u32le_inc(&wrptr, cfg.duty); - ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); + ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty); + sr_err("Cannot setup PWM%d configuration %d %d.", + which, cfg.period, cfg.duty); return ret; } + setting = &devc->pwm_setting[which - 1]; setting->freq = freq; setting->duty = duty; @@ -357,28 +488,27 @@ static int set_defaults(const struct sr_dev_inst *sdi) devc = sdi->priv; - devc->capture_ratio = 5; /* percent */ - devc->cur_channels = 0xffff; - devc->limit_samples = 5000000; - devc->cur_samplerate = SR_MHZ(100); + devc->capture_ratio = LA2016_DFLT_CAPT_RATIO; + devc->limit_samples = LA2016_DFLT_SAMPLEDEPTH; + devc->cur_samplerate = LA2016_DFLT_SAMPLERATE; ret = set_threshold_voltage(sdi, devc->threshold_voltage); if (ret) return ret; - ret = enable_pwm(sdi, 0, 0); + ret = enable_pwm(sdi, FALSE, FALSE); if (ret) return ret; - ret = set_pwm(sdi, 1, 1e3, 50); + ret = configure_pwm(sdi, 1, SR_KHZ(1), 50); if (ret) return ret; - ret = set_pwm(sdi, 2, 100e3, 50); + ret = configure_pwm(sdi, 2, SR_KHZ(100), 50); if (ret) return ret; - ret = enable_pwm(sdi, 1, 1); + ret = enable_pwm(sdi, TRUE, TRUE); if (ret) return ret; @@ -389,7 +519,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; struct sr_trigger *trigger; - trigger_cfg_t cfg; + struct trigger_cfg cfg; GSList *stages; GSList *channel; struct sr_trigger_stage *stage1; @@ -416,7 +546,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) channel = stage1->matches; while (channel) { match = channel->data; - ch_mask = 1 << match->channel->index; + ch_mask = 1UL << match->channel->index; switch (match->match) { case SR_TRIGGER_ZERO: @@ -429,7 +559,7 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) break; case SR_TRIGGER_RISING: if ((cfg.enabled & ~cfg.level)) { - sr_err("Only one trigger signal with falling-/rising-edge allowed."); + sr_err("Device only supports one edge trigger."); return SR_ERR; } cfg.level &= ~ch_mask; @@ -437,35 +567,41 @@ static int set_trigger_config(const struct sr_dev_inst *sdi) break; case SR_TRIGGER_FALLING: if ((cfg.enabled & ~cfg.level)) { - sr_err("Only one trigger signal with falling-/rising-edge allowed."); + sr_err("Device only supports one edge trigger."); return SR_ERR; } cfg.level &= ~ch_mask; cfg.high_or_falling |= ch_mask; break; default: - sr_err("Unknown trigger value."); + sr_err("Unknown trigger condition."); return SR_ERR; } cfg.enabled |= ch_mask; channel = channel->next; } } - sr_dbg("set trigger configuration channels: 0x%04x, " - "trigger-enabled 0x%04x, level-triggered 0x%04x, " - "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level, - cfg.high_or_falling); + sr_dbg("Set trigger config: " + "channels 0x%04x, trigger-enabled 0x%04x, " + "level-triggered 0x%04x, high/falling 0x%04x.", + cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); - devc->had_triggers_configured = cfg.enabled != 0; + devc->trigger_involved = cfg.enabled != 0; wrptr = buf; write_u32le_inc(&wrptr, cfg.channels); write_u32le_inc(&wrptr, cfg.enabled); write_u32le_inc(&wrptr, cfg.level); write_u32le_inc(&wrptr, cfg.high_or_falling); + /* TODO + * Comment on this literal 16. Origin, meaning? Cannot be the + * register offset, nor the transfer length. Is it a channels + * count that is relevant for 16 and 32 channel models? Is it + * an obsolete experiment? + */ ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting trigger config!"); + sr_err("Cannot setup trigger configuration."); return ret; } @@ -476,115 +612,181 @@ static int set_sample_config(const struct sr_dev_inst *sdi) { struct dev_context *devc; double clock_divisor; - uint64_t total; - int ret; - uint16_t divisor; - uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; + uint16_t divider_u16; + uint64_t pre_trigger_samples; + uint64_t pre_trigger_memory; + uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ uint8_t *wrptr; + int ret; devc = sdi->priv; - total = 128 * 1024 * 1024; if (devc->cur_samplerate > devc->max_samplerate) { - sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate); + sr_err("Too high a sample rate: %" PRIu64 ".", + devc->cur_samplerate); return SR_ERR; } clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; - if (clock_divisor > 0xffff) - clock_divisor = 0xffff; - divisor = (uint16_t)(clock_divisor + 0.5); - devc->cur_samplerate = devc->max_samplerate / divisor; + if (clock_divisor > 65535) + return SR_ERR_ARG; + divider_u16 = (uint16_t)(clock_divisor + 0.5); + devc->cur_samplerate = devc->max_samplerate / divider_u16; if (devc->limit_samples > MAX_SAMPLE_DEPTH) { - sr_err("too high sample depth: %" PRIu64, devc->limit_samples); + sr_err("Too high a sample depth: %" PRIu64 ".", + devc->limit_samples); return SR_ERR; } - devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; + /* + * The acquisition configuration communicates "pre-trigger" + * specs in several formats. sigrok users provide a percentage + * (0-100%), which translates to a pre-trigger samples count + * (assuming that a total samples count limit was specified). + * The device supports hardware compression, which depends on + * slowly changing input data to be effective. Fast changing + * input data may occupy more space in sample memory than its + * uncompressed form would. This is why a third parameter can + * limit the amount of sample memory to use for pre-trigger + * data. Only the upper 24 bits of that memory size spec get + * communicated to the device (written to its FPGA register). + */ + pre_trigger_samples = devc->limit_samples * devc->capture_ratio / 100; + pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE; + pre_trigger_memory *= devc->capture_ratio; + pre_trigger_memory /= 100; - sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%", - devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio); + sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", + devc->cur_samplerate / 1000, devc->limit_samples); + sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", + devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); + /* + * The acquisition configuration occupies a total of 16 bytes: + * - A 34bit total samples count limit (up to 10 billions) that + * is kept in a 40bit register. + * - A 34bit pre-trigger samples count limit (up to 10 billions) + * in another 40bit register. + * - A 32bit pre-trigger memory space limit (in bytes) of which + * the upper 24bits are kept in an FPGA register. + * - A 16bit clock divider which gets applied to the maximum + * samplerate of the device. + * - An 8bit register of unknown meaning. Currently always 0. + */ wrptr = buf; - write_u32le_inc(&wrptr, devc->limit_samples); - write_u8_inc(&wrptr, 0); - write_u32le_inc(&wrptr, devc->pre_trigger_size); - write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00 ); - write_u16le_inc(&wrptr, divisor); + write_u40le_inc(&wrptr, devc->limit_samples); + write_u40le_inc(&wrptr, pre_trigger_samples); + write_u24le_inc(&wrptr, pre_trigger_memory >> 8); + write_u16le_inc(&wrptr, divider_u16); write_u8_inc(&wrptr, 0); - ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); if (ret != SR_OK) { - sr_err("error setting sample config!"); + sr_err("Cannot setup acquisition configuration."); return ret; } return SR_OK; } -/* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] - * and the bits are interpreted as follows: - * - * register 0: - * bit0 1= idle - * bit1 1= writing to sdram - * bit2 0= waiting_for_trigger 1=been_triggered - * bit3 0= pretrigger_sampling 1=posttrigger_sampling - * ...unknown... - * register 1: - * meaning of bits unknown (but vendor software reads this, so just do the same) +/* + * FPGA register REG_RUN holds the run state (u16le format). Bit fields + * of interest: + * bit 0: value 1 = idle + * bit 1: value 1 = writing to SDRAM + * bit 2: value 0 = waiting for trigger, 1 = trigger seen + * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling + * The meaning of other bit fields is unknown. * - * The run state values occur in this order: - * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) - * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) - * 0x85EE: running - * 0x85ED: idle + * Typical values in order of appearance during execution: + * 0x85e1: idle, no acquisition pending + * IDLE set, TRGD don't care, POST don't care; DRAM don't care + * "In idle state." Takes precedence over all others. + * 0x85e2: pre-sampling, samples before the trigger position, + * when capture ratio > 0% + * IDLE clear, TRGD clear, POST clear; DRAM don't care + * "Not idle any more, no post yet, not triggered yet." + * 0x85ea: pre-sampling complete, now waiting for the trigger + * (whilst sampling continuously) + * IDLE clear, TRGD clear, POST set; DRAM don't care + * "Post set thus after pre, not triggered yet" + * 0x85ee: trigger seen, capturing post-trigger samples, running + * IDLE clear, TRGD set, POST set; DRAM don't care + * "Triggered and in post, not idle yet." + * 0x85ed: idle + * IDLE set, TRGD don't care, POST don't care; DRAM don't care + * "In idle state." TRGD/POST don't care, same meaning as above. */ +static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; +static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; +static const uint16_t runstate_mask_step = + RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; +static const uint16_t runstate_patt_pre_trig = 0; +static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; +static const uint16_t runstate_patt_post_trig = + RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; + static uint16_t run_state(const struct sr_dev_inst *sdi) { - uint16_t state; - static uint16_t previous_state=0; + static uint16_t previous_state; + int ret; + uint16_t state; + uint8_t buff[sizeof(state)]; + const uint8_t *rdptr; + const char *label; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { - sr_err("failed to read run state!"); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); + if (ret != SR_OK) { + sr_err("Cannot read run state."); return ret; } + rdptr = buff; + state = read_u16le_inc(&rdptr); - /* This function is called about every 50ms. - * To avoid filling the log file with redundant information during long captures, - * just print a log message if status has changed. + /* + * Avoid flooding the log, only dump values as they change. + * The routine is called about every 50ms. */ - - if(state != previous_state) { - previous_state = state; - if((state & 0x0003)==1) { - sr_dbg("run_state: 0x%04x (%s)", state, "idle"); - } - else if((state & 0x000f)==2) { - sr_dbg("run_state: 0x%04x (%s)", state, "pre-trigger sampling"); - } - else if((state & 0x000f)==0x0a) { - sr_dbg("run_state: 0x%04x (%s)", state, "sampling, waiting for trigger"); - } - else if((state & 0x000f)==0x0e) { - sr_dbg("run_state: 0x%04x (%s)", state, "post-trigger sampling"); - } - else { - sr_dbg("run_state: 0x%04x", state); - } - } + if (state == previous_state) + return state; + + previous_state = state; + label = NULL; + if ((state & runstate_mask_idle) == runstate_patt_idle) + label = "idle"; + if ((state & runstate_mask_step) == runstate_patt_pre_trig) + label = "pre-trigger sampling"; + if ((state & runstate_mask_step) == runstate_patt_wait_trig) + label = "sampling, waiting for trigger"; + if ((state & runstate_mask_step) == runstate_patt_post_trig) + label = "post-trigger sampling"; + if (label && *label) + sr_dbg("Run state: 0x%04x (%s).", state, label); + else + sr_dbg("Run state: 0x%04x.", state); return state; } -static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) +static int la2016_is_idle(const struct sr_dev_inst *sdi) +{ + uint16_t state; + + state = run_state(sdi); + if ((state & runstate_mask_idle) == runstate_patt_idle) + return 1; + + return 0; +} + +static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) { int ret; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { - sr_err("failed to send set-run-mode command %d", fast_blinking); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); + if (ret != SR_OK) { + sr_err("Cannot configure run mode %d.", mode); return ret; } @@ -600,8 +802,9 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc = sdi->priv; - if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { - sr_err("failed to read capture info!"); + ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); + if (ret != SR_OK) { + sr_err("Cannot read capture info."); return ret; } @@ -610,18 +813,23 @@ static int get_capture_info(const struct sr_dev_inst *sdi) devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); devc->info.write_pos = read_u32le_inc(&rdptr); - sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d", - devc->info.n_rep_packets, devc->info.n_rep_packets, - devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger, - devc->info.write_pos, devc->info.write_pos); + sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", + devc->info.n_rep_packets, devc->info.n_rep_packets, + devc->info.n_rep_packets_before_trigger, + devc->info.n_rep_packets_before_trigger, + devc->info.write_pos, devc->info.write_pos); - if (devc->info.n_rep_packets % 5) - sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets); + if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { + sr_warn("Unexpected packets count %lu, not a multiple of %d.", + (unsigned long)devc->info.n_rep_packets, + NUM_PACKETS_IN_CHUNK); + } return SR_OK; } -SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) +SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, + libusb_device *dev, uint16_t product_id) { char fw_file[1024]; snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); @@ -641,8 +849,9 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) return ret; cmd = 0; - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { - sr_err("failed to send stop sampling command"); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); + if (ret != SR_OK) { + sr_err("Cannot send command to stop sampling."); return ret; } @@ -659,29 +868,44 @@ SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 3); + int ret; + + ret = set_run_mode(sdi, RUNMODE_RUN); + if (ret != SR_OK) + return ret; + + return SR_OK; } -SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi) +static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) { - return set_run_mode(sdi, 0); + int ret; + + ret = set_run_mode(sdi, RUNMODE_HALT); + if (ret != SR_OK) + return ret; + + return SR_OK; } SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) { - return la2016_stop_acquisition(sdi); -} + int ret; + struct dev_context *devc; -SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi) -{ - uint16_t state; + ret = la2016_stop_acquisition(sdi); + if (ret != SR_OK) + return ret; - state = run_state(sdi); + devc = sdi ? sdi->priv : NULL; + if (devc && devc->transfer) + libusb_cancel_transfer(devc->transfer); - return (state & 0x3) == 1; + return SR_OK; } -SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) +static int la2016_start_download(const struct sr_dev_inst *sdi, + libusb_transfer_cb_fn cb) { struct dev_context *devc; struct sr_usb_dev_inst *usb; @@ -694,7 +918,8 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe devc = sdi->priv; usb = sdi->conn; - if ((ret = get_capture_info(sdi)) != SR_OK) + ret = get_capture_info(sdi); + if (ret != SR_OK) return ret; devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; @@ -702,44 +927,55 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; - sr_dbg("want to read %d tfer-packets starting from pos %d", - devc->n_transfer_packets_to_read, devc->read_pos); + sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", + devc->n_transfer_packets_to_read, devc->read_pos); - if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to reset bulk state"); + ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); + if (ret != SR_OK) { + sr_err("Cannot reset USB bulk state."); return ret; } - sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read); + sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", + (unsigned long)devc->read_pos, devc->n_bytes_to_read); wrptr = wrbuf; write_u32le_inc(&wrptr, devc->read_pos); write_u32le_inc(&wrptr, devc->n_bytes_to_read); - if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { - sr_err("failed to send bulk config"); + ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); + if (ret != SR_OK) { + sr_err("Cannot send USB bulk config."); return ret; } - if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to unblock bulk transfers"); + ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); + if (ret != SR_OK) { + sr_err("Cannot unblock USB bulk transfers."); return ret; } + /* + * Pick a buffer size for all USB transfers. The buffer size + * must be a multiple of the endpoint packet size. And cannot + * exceed a maximum value. + */ to_read = devc->n_bytes_to_read; - if (to_read > LA2016_BULK_MAX) - to_read = LA2016_BULK_MAX; - + if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ + to_read = LA2016_USB_BUFSZ; + else /* One transfer. */ + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); buffer = g_try_malloc(to_read); if (!buffer) { - sr_err("Failed to allocate %d bytes for bulk transfer", to_read); + sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); + sr_err("Cannot allocate buffer for USB bulk transfer."); return SR_ERR_MALLOC; } devc->transfer = libusb_alloc_transfer(0); - libusb_fill_bulk_transfer( - devc->transfer, usb->devhdl, - 0x86, buffer, to_read, - cb, (void *)sdi, DEFAULT_TIMEOUT_MS); + libusb_fill_bulk_transfer(devc->transfer, + usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, + buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); - if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { - sr_err("Failed to submit transfer: %s.", libusb_error_name(ret)); + ret = libusb_submit_transfer(devc->transfer); + if (ret != 0) { + sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); libusb_free_transfer(devc->transfer); devc->transfer = NULL; g_free(buffer); @@ -749,123 +985,356 @@ SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfe return SR_OK; } +/* + * A chunk (received via USB) contains a number of transfers (USB length + * divided by 16) which contain a number of packets (5 per transfer) which + * contain a number of samples (8bit repeat count per 16bit sample data). + */ +static void send_chunk(struct sr_dev_inst *sdi, + const uint8_t *packets, size_t num_xfers) +{ + struct dev_context *devc; + struct sr_datafeed_logic logic; + struct sr_datafeed_packet sr_packet; + unsigned int max_samples, n_samples, total_samples, free_n_samples; + size_t num_pkts; + gboolean do_signal_trigger; + uint8_t *wp; + const uint8_t *rp; + uint16_t sample_value; + size_t repetitions; + uint8_t sample_buff[sizeof(sample_value)]; + + devc = sdi->priv; + + logic.unitsize = sizeof(sample_buff); + logic.data = devc->convbuffer; + + sr_packet.type = SR_DF_LOGIC; + sr_packet.payload = &logic; + + max_samples = devc->convbuffer_size / sizeof(sample_buff); + n_samples = 0; + wp = devc->convbuffer; + total_samples = 0; + do_signal_trigger = FALSE; + + if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { + std_session_send_df_trigger(sdi); + devc->trigger_marked = TRUE; + } + + rp = packets; + while (num_xfers--) { + num_pkts = NUM_PACKETS_IN_CHUNK; + while (num_pkts--) { + /* + * Flush the conversion buffer when a trigger + * location needs to get communicated, or when + * an to-get-expected sample repetition count + * would no longer fit into the buffer. + */ + free_n_samples = max_samples - n_samples; + if (free_n_samples < 256 || do_signal_trigger) { + logic.length = n_samples * sizeof(sample_buff);; + sr_session_send(sdi, &sr_packet); + n_samples = 0; + wp = devc->convbuffer; + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + do_signal_trigger = FALSE; + } + } + + sample_value = read_u16le_inc(&rp); + repetitions = read_u8_inc(&rp); + + n_samples += repetitions; + total_samples += repetitions; + devc->total_samples += repetitions; + + write_u16le(sample_buff, sample_value); + while (repetitions--) { + memcpy(wp, sample_buff, logic.unitsize); + wp += logic.unitsize; + } + + if (devc->trigger_involved && !devc->trigger_marked) { + if (!--devc->n_reps_until_trigger) { + devc->trigger_marked = TRUE; + do_signal_trigger = TRUE; + sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", + devc->total_samples, + (double)devc->total_samples / devc->cur_samplerate * 1e3); + } + } + } + (void)read_u8_inc(&rp); /* Skip sequence number. */ + } + if (n_samples) { + logic.length = n_samples * logic.unitsize; + sr_session_send(sdi, &sr_packet); + if (do_signal_trigger) { + std_session_send_df_trigger(sdi); + } + } + sr_dbg("Send_chunk done after %u samples.", total_samples); +} + +static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) +{ + struct sr_dev_inst *sdi; + struct dev_context *devc; + struct sr_usb_dev_inst *usb; + int ret; + + sdi = transfer->user_data; + devc = sdi->priv; + usb = sdi->conn; + + sr_dbg("receive_transfer(): status %s received %d bytes.", + libusb_error_name(transfer->status), transfer->actual_length); + + if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { + sr_err("USB bulk transfer timeout."); + devc->download_finished = TRUE; + } + send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); + + devc->n_bytes_to_read -= transfer->actual_length; + if (devc->n_bytes_to_read) { + uint32_t to_read = devc->n_bytes_to_read; + /* + * Determine read size for the next USB transfer. Make + * the buffer size a multiple of the endpoint packet + * size. Don't exceed a maximum value. + */ + if (to_read >= LA2016_USB_BUFSZ) + to_read = LA2016_USB_BUFSZ; + else + to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); + libusb_fill_bulk_transfer(transfer, + usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, + transfer->buffer, to_read, + receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); + + ret = libusb_submit_transfer(transfer); + if (ret == 0) + return; + sr_err("Cannot submit another USB transfer: %s.", + libusb_error_name(ret)); + } + + g_free(transfer->buffer); + libusb_free_transfer(transfer); + devc->download_finished = TRUE; +} + +SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) +{ + const struct sr_dev_inst *sdi; + struct dev_context *devc; + struct drv_context *drvc; + struct timeval tv; + + (void)fd; + (void)revents; + + sdi = cb_data; + devc = sdi->priv; + drvc = sdi->driver->context; + + if (!devc->completion_seen) { + if (!la2016_is_idle(sdi)) { + /* Not yet ready for sample data download. */ + return TRUE; + } + devc->completion_seen = TRUE; + devc->download_finished = FALSE; + devc->trigger_marked = FALSE; + devc->total_samples = 0; + /* We can start downloading sample data. */ + if (la2016_start_download(sdi, receive_transfer) != SR_OK) { + sr_err("Cannot start acquisition data download."); + return FALSE; + } + sr_dbg("Acquisition data download started."); + std_session_send_df_frame_begin(sdi); + + return TRUE; + } + + tv.tv_sec = tv.tv_usec = 0; + libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); + + if (devc->download_finished) { + sr_dbg("Download finished, post processing."); + std_session_send_df_frame_end(sdi); + + usb_source_remove(sdi->session, drvc->sr_ctx); + std_session_send_df_end(sdi); + + la2016_stop_acquisition(sdi); + + g_free(devc->convbuffer); + devc->convbuffer = NULL; + + devc->transfer = NULL; + + sr_dbg("Download finished, done post processing."); + } + + return TRUE; +} + SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) { struct dev_context *devc; uint16_t state; uint8_t buf[8]; - int16_t purchase_date_bcd[2]; + const uint8_t *rdptr; + uint8_t date_yy, date_mm; + uint8_t dinv_yy, dinv_mm; uint8_t magic; + const char *bitstream_fn; int ret; devc = sdi->priv; - /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit - * complemented checksum; e.g. 2004DFFB = 2020-April. - * This helps to identify the age of devices if unknown magic numbers occur. + /* + * Four EEPROM bytes at offset 0x20 are the manufacturing date, + * year and month in BCD format, followed by inverted values for + * consistency checks. For example bytes 20 04 df fb translate + * to 2020-04. This information can help identify the vintage of + * devices when unknown magic numbers are seen. */ - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { - sr_err("failed to read eeprom purchase_date_bcd"); - } - else { - sr_dbg("purchase date: 20%02hx-%02hx", (purchase_date_bcd[0]) & 0x00ff, (purchase_date_bcd[0] >> 8) & 0x00ff); - if( purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1]) ) { - sr_err("purchase date: checksum failure"); - } + ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t)); + if (ret != SR_OK) { + sr_err("Cannot read manufacture date in EEPROM."); + } else { + rdptr = &buf[0]; + date_yy = read_u8_inc(&rdptr); + date_mm = read_u8_inc(&rdptr); + dinv_yy = read_u8_inc(&rdptr); + dinv_mm = read_u8_inc(&rdptr); + sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); + if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) + sr_warn("Manufacture date fails checksum test."); } /* - * There are four known kingst logic analyser devices which use this same usb vid and pid: - * LA2016, LA1016 and the older revision of each of these. They all use the same hardware - * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are - * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. - * For example; + * Several Kingst logic analyzer devices share the same USB VID + * and PID. The product ID determines which MCU firmware to load. + * The MCU firmware provides access to EEPROM content which then + * allows to identify the device model. Which in turn determines + * which FPGA bitstream to load. Eight bytes at offset 0x08 are + * to get inspected. * - * magic=0x08 - * | ~magic=0xf7 - * | | - * 08F7000008F710EF - * | | - * | ~magic-backup - * magic-backup + * EEPROM content for model identification is kept redundantly + * in memory. The values are stored in verbatim and in inverted + * form, multiple copies are kept at different offsets. Example + * data: * - * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. - * Changing the magic byte on newer device to older magic causes OEM software to load - * the older fpga bitstream. The device then functions but has channels out of order. - * It's likely the bitstreams were changed to move input channel pins due to PCB changes. + * magic 0x08 + * | ~magic 0xf7 + * | | + * 08f7000008f710ef + * | | + * | ~magic backup + * magic backup * - * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) - * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) - * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" - * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" + * Exclusively inspecting the magic byte appears to be sufficient, + * other fields seem to be 'don't care'. * - * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing - * the vendor software actions, either raising errors or loading specific bitstreams. + * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" + * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" + * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) + * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" + * (latest v1.3.0 PCB, perhaps others) * - * Note: - * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream - * will not authenticate with ic U10, which has different security coding for each device type. + * When EEPROM content does not match the hardware configuration + * (the board layout), the software may load but yield incorrect + * results (like swapped channels). The FPGA bitstream itself + * will authenticate with IC U10 and fail when its capabilities + * do not match the hardware model. An LA1016 won't become a + * LA2016 by faking its EEPROM content. */ - if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { - sr_err("failed to read eeprom device identifier bytes"); + sr_err("Cannot read EEPROM device identifier bytes."); return ret; } - - magic = 0; - if (buf[0] == (0x0ff & ~buf[1])) { - /* primary copy of magic passes complement check */ + if ((buf[0] ^ buf[1]) == 0xff) { + /* Primary copy of magic passes complement check. */ + sr_dbg("Using primary copy of device type magic number."); magic = buf[0]; - } - else if (buf[4] == (0x0ff & ~buf[5])) { - /* backup copy of magic passes complement check */ - sr_dbg("device_type: using backup copy of magic number"); + } else if ((buf[4] ^ buf[5]) == 0xff) { + /* Backup copy of magic passes complement check. */ + sr_dbg("Using backup copy of device type magic number."); magic = buf[4]; + } else { + sr_err("Cannot find consistent device type identification."); + magic = 0; } + sr_dbg("Device type: magic number is %hhu.", magic); - sr_dbg("device_type: magic number is %hhu", magic); - - /* select the correct fpga bitstream for this device */ + /* Select the FPGA bitstream depending on the model. */ switch (magic) { case 2: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); + bitstream_fn = FPGA_FW_LA2016; devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; break; case 3: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); + bitstream_fn = FPGA_FW_LA1016; devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; case 8: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); + bitstream_fn = FPGA_FW_LA2016A; devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; break; case 9: - ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); + bitstream_fn = FPGA_FW_LA1016A; devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; break; default: - sr_err("device_type: device not supported; magic number indicates this is not a LA2016 or LA1016"); + bitstream_fn = NULL; + break; + } + if (!bitstream_fn || !*bitstream_fn) { + sr_err("Cannot identify as one of the supported models."); return SR_ERR; } + if (check_fpga_bitstream(sdi) != SR_OK) { + ret = upload_fpga_bitstream(sdi, bitstream_fn); + if (ret != SR_OK) { + sr_err("Cannot upload FPGA bitstream."); + return ret; + } + } + ret = enable_fpga_bitstream(sdi); if (ret != SR_OK) { - sr_err("failed to upload fpga bitstream"); + sr_err("Cannot enable FPGA bitstream after upload."); return ret; } state = run_state(sdi); if (state != 0x85e9) { - sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state); + sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); } if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to send CMD_BULK_RESET"); + sr_err("Cannot reset USB bulk transfer."); return ret; } - sr_dbg("device should be initialized"); + sr_dbg("Device should be initialized."); + + ret = set_defaults(sdi); + if (ret != SR_OK) + return ret; - return set_defaults(sdi); + return SR_OK; } SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) @@ -873,7 +1342,7 @@ SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) int ret; if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { - sr_err("failed to send deinit command"); + sr_err("Cannot deinitialize device's FPGA."); return ret; }