X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fhantek-4032l%2Fprotocol.h;h=15a0951cb0885726bfb03335491b492f6552b821;hb=bf2a6eeaa078650de53372903d2a3b5520a668bd;hp=8665c8f08e83efab5139f5a523731885a73835c0;hpb=3dc976fe9fcc21a1b82087fe6b969cf997346bdc;p=libsigrok.git

diff --git a/src/hardware/hantek-4032l/protocol.h b/src/hardware/hantek-4032l/protocol.h
index 8665c8f0..15a0951c 100644
--- a/src/hardware/hantek-4032l/protocol.h
+++ b/src/hardware/hantek-4032l/protocol.h
@@ -44,6 +44,26 @@
 #define H4032L_START_PACKET_MAGIC 0x2B1A027F
 #define H4032L_END_PACKET_MAGIC 0x4D3C037F
 
+enum h4032l_clock_edge_type {
+	H4032L_CLOCK_EDGE_TYPE_RISE,
+	H4032L_CLOCK_EDGE_TYPE_FALL,
+	H4032L_CLOCK_EDGE_TYPE_BOTH
+};
+
+enum h4032l_ext_clock_source {
+	H4032L_EXT_CLOCK_SOURCE_CHANNEL_A,
+	H4032L_EXT_CLOCK_SOURCE_CHANNEL_B
+};
+
+enum h4032l_clock_edge_type_channel {
+	H4032L_CLOCK_EDGE_TYPE_RISE_A = 0x24,
+	H4032L_CLOCK_EDGE_TYPE_RISE_B,
+	H4032L_CLOCK_EDGE_TYPE_BOTH_A,
+	H4032L_CLOCK_EDGE_TYPE_BOTH_B,
+	H4032L_CLOCK_EDGE_TYPE_FALL_A,
+	H4032L_CLOCK_EDGE_TYPE_FALL_B
+};
+
 enum h4032l_trigger_edge_type {
 	H4032L_TRIGGER_EDGE_TYPE_RISE,
 	H4032L_TRIGGER_EDGE_TYPE_FALL,
@@ -126,6 +146,7 @@ struct h4032l_cmd_pkt {
 
 struct dev_context {
 	enum h4032l_status status;
+	uint64_t sample_rate;
 	unsigned int sent_samples;
 	int submitted_transfers;
 	uint32_t remaining_samples;
@@ -133,9 +154,13 @@ struct dev_context {
 	struct h4032l_cmd_pkt cmd_pkt;
 	unsigned int num_transfers;
 	struct libusb_transfer **transfers;
-	uint8_t buffer[512];
+	uint8_t buf[512];
 	uint64_t capture_ratio;
 	uint32_t trigger_pos;
+	gboolean external_clock;
+	enum h4032l_ext_clock_source external_clock_source;
+	enum h4032l_clock_edge_type clock_edge;
+	double cur_threshold[2];
 	uint32_t fpga_version;
 };