X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fhantek-4032l%2Fapi.c;h=7e823f8c7935cb9eb1422fcc6e1fdb5b389f991c;hb=821266e8ed4116e08f2a64561cc570c47b5a4b40;hp=729a85da6204910c1298ab2f2a16146de060cea5;hpb=bf2a6eeaa078650de53372903d2a3b5520a668bd;p=libsigrok.git

diff --git a/src/hardware/hantek-4032l/api.c b/src/hardware/hantek-4032l/api.c
index 729a85da..7e823f8c 100644
--- a/src/hardware/hantek-4032l/api.c
+++ b/src/hardware/hantek-4032l/api.c
@@ -167,7 +167,7 @@ static const uint64_t samplerates_hw[] = {
 	SR_MHZ(320),
 };
 
-SR_PRIV struct sr_dev_driver hantek_4032l_driver_info;
+static struct sr_dev_driver hantek_4032l_driver_info;
 
 static GSList *scan(struct sr_dev_driver *di, GSList *options)
 {
@@ -233,10 +233,9 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 
 		struct sr_channel_group *channel_groups[2];
 		for (int j = 0; j < 2; j++) {
-			cg = g_malloc0(sizeof(struct sr_channel_group));
+			cg = sr_channel_group_new(sdi, NULL, NULL);
 			cg->name = g_strdup_printf("%c", 'A' + j);
 			channel_groups[j] = cg;
-			sdi->channel_groups = g_slist_append(sdi->channel_groups, cg);
 		}
 
 		/* Assemble channel list and add channel to channel groups. */
@@ -261,8 +260,13 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 		devc->external_clock = FALSE;
 		devc->clock_edge = H4032L_CLOCK_EDGE_TYPE_RISE;
 
-		devc->cur_threshold[0] = 2.5;
-		devc->cur_threshold[1] = 2.5;
+		/* Create array of thresholds from min to max. */
+		GVariant *thresholds = std_gvar_min_max_step_thresholds(
+			H4032L_THR_VOLTAGE_MIN, H4032L_THR_VOLTAGE_MAX,
+			H4032L_THR_VOLTAGE_STEP);
+		/* Take default threshold value from array (FP workaround). */
+		g_variant_get_child(thresholds, H4032L_THR_VOLTAGE_DEFAULT,
+			"(dd)", &devc->cur_threshold[0], &devc->cur_threshold[1]);
 
 		sdi->priv = devc;
 		devices = g_slist_append(devices, sdi);
@@ -468,7 +472,8 @@ static int config_list(uint32_t key, GVariant **data,
 		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
 		break;
 	case SR_CONF_VOLTAGE_THRESHOLD:
-		*data = std_gvar_min_max_step_thresholds(-6.0, 6.0, 0.1);
+		*data = std_gvar_min_max_step_thresholds(H4032L_THR_VOLTAGE_MIN,
+			H4032L_THR_VOLTAGE_MAX, H4032L_THR_VOLTAGE_STEP);
 		break;
 	case SR_CONF_LIMIT_SAMPLES:
 		*data = std_gvar_tuple_u64(H4043L_NUM_SAMPLES_MIN, H4032L_NUM_SAMPLES_MAX);
@@ -509,7 +514,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 	else
 		cmd_pkt->sample_rate = devc->sample_rate;
 
-	/* Set pwm channel values. */
+	/* Set PWM channel values. */
 	devc->cmd_pkt.pwm_a = h4032l_voltage2pwm(devc->cur_threshold[0]);
 	devc->cmd_pkt.pwm_b = h4032l_voltage2pwm(devc->cur_threshold[1]);
 
@@ -581,25 +586,9 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
 			channel = channel->next;
 		}
 
-		/* Compress range mask value and apply range settings. */
-		if (range_mask) {
-			cmd_pkt->trigger[0].flags.data_range_enabled = 1;
-			cmd_pkt->trigger[0].data_range_mask |= (range_mask);
-
-			uint32_t new_range_value = 0;
-			uint32_t bit_mask = 1;
-			while (range_mask) {
-				if ((range_mask & 1) != 0) {
-					new_range_value <<= 1;
-					if ((range_value & 1) != 0)
-						new_range_value |= bit_mask;
-					bit_mask <<= 1;
-				}
-				range_mask >>= 1;
-				range_value >>= 1;
-			}
-			cmd_pkt->trigger[0].data_range_max |= range_value;
-		}
+		cmd_pkt->trigger[0].flags.data_range_enabled = 1;
+		cmd_pkt->trigger[0].data_range_mask |= range_mask;
+		cmd_pkt->trigger[0].data_range_max = range_value;
 	}
 
 	usb_source_add(sdi->session, drvc->sr_ctx, 1000,
@@ -615,7 +604,7 @@ static int dev_acquisition_stop(struct sr_dev_inst *sdi)
 	return h4032l_stop(sdi);
 }
 
-SR_PRIV struct sr_dev_driver hantek_4032l_driver_info = {
+static struct sr_dev_driver hantek_4032l_driver_info = {
 	.name = "hantek-4032l",
 	.longname = "Hantek 4032L",
 	.api_version = 1,