X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Ffx2lafw%2Fdslogic.h;h=f74367ade59499de7d2811b2f2767a5aec7c6c57;hb=d431e4ec28d5d168bc0d98d5545a585b89d52e8d;hp=411e8331be8e84df8684b9d2171d3456ede6acb5;hpb=3f0ff4128447a7fc1e0105b85cdc9cfcf831dafc;p=libsigrok.git

diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 411e8331..f74367ad 100644
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -27,11 +27,16 @@
 #define DS_CMD_START			0xb2
 #define DS_CMD_FPGA_FW			0xb3
 #define DS_CMD_CONFIG			0xb4
+#define DS_CMD_VTH			0xb8
 
 #define DS_NUM_TRIGGER_STAGES		16
 #define DS_START_FLAGS_STOP		(1 << 7)
 #define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
 #define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)
+#define DS_START_FLAGS_MODE_LA		(1 << 4)
+
+#define DS_MAX_LOGIC_DEPTH		SR_MHZ(16)
+#define DS_MAX_LOGIC_SAMPLERATE		SR_MHZ(100)
 
 enum dslogic_operation_modes {
 	DS_OP_NORMAL,
@@ -40,6 +45,16 @@ enum dslogic_operation_modes {
 	DS_OP_LOOPBACK_TEST,
 };
 
+enum {
+	DS_VOLTAGE_RANGE_18_33_V,	/* 1.8V and 3.3V logic */
+	DS_VOLTAGE_RANGE_5_V,		/* 5V logic */
+};
+
+enum {
+	DS_EDGE_RISING,
+	DS_EDGE_FALLING,
+};
+
 struct dslogic_version {
 	uint8_t major;
 	uint8_t minor;
@@ -54,7 +69,8 @@ struct dslogic_mode {
 struct dslogic_trigger_pos {
 	uint32_t real_pos;
 	uint32_t ram_saddr;
-	uint8_t first_block[504];
+	uint32_t remain_cnt;
+	uint8_t first_block[500];
 };
 
 /*
@@ -128,5 +144,7 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
+SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
 
 #endif