X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Ffx2lafw%2Fdslogic.h;h=f74367ade59499de7d2811b2f2767a5aec7c6c57;hb=d431e4ec28d5d168bc0d98d5545a585b89d52e8d;hp=4070eea70337d066e45f7a26b14a9dfc9a214777;hpb=b9d530920fa97ab92d5f78f6f00a1ffc73259f2f;p=libsigrok.git

diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 4070eea7..f74367ad 100644
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -18,17 +18,25 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
+#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
+
 /* Modified protocol commands & flags used by DSLogic */
 #define DS_CMD_GET_FW_VERSION		0xb0
 #define DS_CMD_GET_REVID_VERSION	0xb1
-#define DS_CMD_START				0xb2
-#define DS_CMD_FPGA_FW				0xb3
-#define DS_CMD_CONFIG				0xb4
+#define DS_CMD_START			0xb2
+#define DS_CMD_FPGA_FW			0xb3
+#define DS_CMD_CONFIG			0xb4
+#define DS_CMD_VTH			0xb8
+
+#define DS_NUM_TRIGGER_STAGES		16
+#define DS_START_FLAGS_STOP		(1 << 7)
+#define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
+#define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)
+#define DS_START_FLAGS_MODE_LA		(1 << 4)
 
-#define DS_NUM_TRIGGER_STAGES	16
-#define DS_START_FLAGS_STOP        (1 << 7)
-#define DS_START_FLAGS_CLK_48MHZ   (1 << 6)
-#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
+#define DS_MAX_LOGIC_DEPTH		SR_MHZ(16)
+#define DS_MAX_LOGIC_SAMPLERATE		SR_MHZ(100)
 
 enum dslogic_operation_modes {
 	DS_OP_NORMAL,
@@ -37,6 +45,16 @@ enum dslogic_operation_modes {
 	DS_OP_LOOPBACK_TEST,
 };
 
+enum {
+	DS_VOLTAGE_RANGE_18_33_V,	/* 1.8V and 3.3V logic */
+	DS_VOLTAGE_RANGE_5_V,		/* 5V logic */
+};
+
+enum {
+	DS_EDGE_RISING,
+	DS_EDGE_FALLING,
+};
+
 struct dslogic_version {
 	uint8_t major;
 	uint8_t minor;
@@ -51,7 +69,8 @@ struct dslogic_mode {
 struct dslogic_trigger_pos {
 	uint32_t real_pos;
 	uint32_t ram_saddr;
-	uint8_t first_block[504];
+	uint32_t remain_cnt;
+	uint8_t first_block[500];
 };
 
 /*
@@ -61,8 +80,8 @@ struct dslogic_trigger_pos {
  */
 #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
 #define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
-#define DS_CFG_START		0xffffffff
-#define DS_CFG_MODE			_DS_CFG(0, 1)
+#define DS_CFG_START		0xf5a5f5a5
+#define DS_CFG_MODE		_DS_CFG(0, 1)
 #define DS_CFG_DIVIDER		_DS_CFG_PAD(1, 2)
 #define DS_CFG_COUNT		_DS_CFG_PAD(3, 2)
 #define DS_CFG_TRIG_POS		_DS_CFG_PAD(5, 2)
@@ -79,7 +98,7 @@ struct dslogic_trigger_pos {
 #define DS_CFG_TRIG_COUNT1	_DS_CFG_PAD(29, 16)
 #define DS_CFG_TRIG_LOGIC0	_DS_CFG_PAD(32, 16)
 #define DS_CFG_TRIG_LOGIC1	_DS_CFG_PAD(33, 16)
-#define DS_CFG_END			0x00000000
+#define DS_CFG_END		0xfa5afa5a
 
 struct dslogic_fpga_config {
 	uint32_t sync;
@@ -120,9 +139,12 @@ struct dslogic_fpga_config {
 	uint32_t end_sync;
 };
 
+SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
+		const char *name);
+SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
+SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
+SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
+SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
 
-int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
-		const char *filename);
-int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
-int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
-int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
+#endif