X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Ffx2lafw%2Fdslogic.c;h=f912278fa23c7505462b50bb700dfd41b25eb70c;hb=cee6d3fa0c9f3326fd8844f0fcb292c3466bc562;hp=ec8d53427b9536e798ad9503657104070dc1963b;hpb=8e2d6c9db788785466d61fdac4d8fdc1535bc20c;p=libsigrok.git

diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index ec8d5342..f912278f 100644
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -25,7 +25,12 @@
 #include "protocol.h"
 #include "dslogic.h"
 
-#define FW_BUFSIZE (4 * 1024)
+/*
+ * This should be larger than the FPGA bitstream image so that it'll get
+ * uploaded in one big operation. There seem to be issues when uploading
+ * it in chunks.
+ */
+#define FW_BUFSIZE (1024 * 1024)
 
 #define FPGA_UPLOAD_DELAY (10 * 1000)
 
@@ -112,7 +117,7 @@ SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
 	int ret;
 
 	devc = sdi->priv;
-	mode.flags = 0;
+	mode.flags = DS_START_FLAGS_MODE_LA;
 	mode.sample_delay_h = mode.sample_delay_l = 0;
 	if (devc->sample_wide)
 		mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
@@ -150,6 +155,100 @@ SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
 	return SR_OK;
 }
 
+/*
+ * Get the session trigger and configure the FPGA structure
+ * accordingly.
+ */
+static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
+	struct dslogic_fpga_config *cfg)
+{
+	struct sr_trigger *trigger;
+	struct sr_trigger_stage *stage;
+	struct sr_trigger_match *match;
+	struct dev_context *devc;
+	const GSList *l, *m;
+	int channelbit, i = 0;
+	uint16_t v16;
+
+	devc = sdi->priv;
+	devc->trigger_en = FALSE;
+
+	cfg->trig_mask0[0] = 0xffff;
+	cfg->trig_mask1[0] = 0xffff;
+
+	cfg->trig_value0[0] = 0;
+	cfg->trig_value1[0] = 0;
+
+	cfg->trig_edge0[0] = 0;
+	cfg->trig_edge1[0] = 0;
+
+	cfg->trig_logic0[0] = 0;
+	cfg->trig_logic1[0] = 0;
+
+	cfg->trig_count0[0] = 0;
+	cfg->trig_count1[0] = 0;
+
+	if (!(trigger = sr_session_trigger_get(sdi->session)))
+		return SR_OK;
+
+	for (l = trigger->stages; l; l = l->next) {
+		stage = l->data;
+		for (m = stage->matches; m; m = m->next) {
+			match = m->data;
+			if (!match->channel->enabled)
+				/* Ignore disabled channels with a trigger. */
+				continue;
+			channelbit = 1 << (match->channel->index);
+			devc->trigger_en = TRUE; /* Triggered. */
+			/* Simple trigger support (event). */
+			if (match->match == SR_TRIGGER_ONE) {
+				cfg->trig_mask0[0] &= ~channelbit;
+				cfg->trig_mask1[0] &= ~channelbit;
+				cfg->trig_value0[0] |= channelbit;
+				cfg->trig_value1[0] |= channelbit;
+			} else if (match->match == SR_TRIGGER_ZERO) {
+				cfg->trig_mask0[0] &= ~channelbit;
+				cfg->trig_mask1[0] &= ~channelbit;
+			} else if (match->match == SR_TRIGGER_FALLING) {
+				cfg->trig_mask0[0] &= ~channelbit;
+				cfg->trig_mask1[0] &= ~channelbit;
+				cfg->trig_edge0[0] |= channelbit;
+				cfg->trig_edge1[0] |= channelbit;
+			} else if (match->match == SR_TRIGGER_RISING) {
+				cfg->trig_mask0[0] &= ~channelbit;
+				cfg->trig_mask1[0] &= ~channelbit;
+				cfg->trig_value0[0] |= channelbit;
+				cfg->trig_value1[0] |= channelbit;
+				cfg->trig_edge0[0] |= channelbit;
+				cfg->trig_edge1[0] |= channelbit;
+			} else if (match->match == SR_TRIGGER_EDGE){
+				cfg->trig_edge0[0] |= channelbit;
+				cfg->trig_edge1[0] |= channelbit;
+			}
+		}
+	}
+
+	if (devc->trigger_en) {
+		for (i = 1; i < 16; i++) {
+			cfg->trig_mask0[i] = 0xff;
+			cfg->trig_mask1[i] = 0xff;
+			cfg->trig_value0[i] = 0;
+			cfg->trig_value1[i] = 0;
+			cfg->trig_edge0[i] = 0;
+			cfg->trig_edge1[i] = 0;
+			cfg->trig_count0[i] = 0;
+			cfg->trig_count1[i] = 0;
+			cfg->trig_logic0[i] = 2;
+			cfg->trig_logic1[i] = 2;
+		}
+		v16 = RL16(&cfg->mode);
+		v16 |= 1 << 0;
+		WL16(&cfg->mode, v16);
+	}
+
+	return SR_OK;
+}
+
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 {
 	struct dev_context *devc;
@@ -202,6 +301,8 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 	 * 15	1 = internal test mode
 	 * 14	1 = external test mode
 	 * 13	1 = loopback test mode
+	 * 12	1 = stream mode
+	 * 11	1 = serial trigger
 	 * 8-12	unused
 	 * 7	1 = analog mode
 	 * 6	1 = samplerate 400MHz
@@ -218,14 +319,16 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 		v16 = 1 << 14;
 	else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
 		v16 = 1 << 13;
-	if (devc->dslogic_external_clock)
-		v16 |= 1 << 2;
+	//if (devc->dslogic_external_clock)
+	//	v16 |= 1 << 1;
+	//v16 |= 1 << 0;
 	WL16(&cfg.mode, v16);
-
 	v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
 	WL32(&cfg.divider, v32);
 	WL32(&cfg.count, devc->limit_samples);
 
+	dslogic_set_trigger(sdi, &cfg);
+
 	len = sizeof(struct dslogic_fpga_config);
 	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);