X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Ffx2lafw%2Fapi.c;h=c3a819b459121966e9e7715d23358e439aff655e;hb=c33f32a9225dcc7cad0577e15d477645baf654cc;hp=1ad9bedc56b3b18e83096d7b646c24510f3fc497;hpb=f9592d65e9759b9a37c51a090c3504d4328ba4d4;p=libsigrok.git

diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c
index 1ad9bedc..c3a819b4 100644
--- a/src/hardware/fx2lafw/api.c
+++ b/src/hardware/fx2lafw/api.c
@@ -57,29 +57,47 @@ static const struct fx2lafw_profile supported_fx2[] = {
 	/* DreamSourceLab DSLogic (before FW upload) */
 	{ 0x2a0e, 0x0001, "DreamSourceLab", "DSLogic", NULL,
 		"dreamsourcelab-dslogic-fx2.fw",
-		DEV_CAPS_16BIT, NULL, NULL},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
 	/* DreamSourceLab DSLogic (after FW upload) */
 	{ 0x2a0e, 0x0001, "DreamSourceLab", "DSLogic", NULL,
 		"dreamsourcelab-dslogic-fx2.fw",
-		DEV_CAPS_16BIT, "DreamSourceLab", "DSLogic"},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", "DSLogic"},
 
 	/* DreamSourceLab DSCope (before FW upload) */
 	{ 0x2a0e, 0x0002, "DreamSourceLab", "DSCope", NULL,
 		"dreamsourcelab-dscope-fx2.fw",
-		DEV_CAPS_16BIT, NULL, NULL},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
 	/* DreamSourceLab DSCope (after FW upload) */
 	{ 0x2a0e, 0x0002, "DreamSourceLab", "DSCope", NULL,
 		"dreamsourcelab-dscope-fx2.fw",
-		DEV_CAPS_16BIT, "DreamSourceLab", "DSCope"},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", "DSCope"},
 
 	/* DreamSourceLab DSLogic Pro (before FW upload) */
 	{ 0x2a0e, 0x0003, "DreamSourceLab", "DSLogic Pro", NULL,
 		"dreamsourcelab-dslogic-pro-fx2.fw",
-		DEV_CAPS_16BIT, NULL, NULL},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
 	/* DreamSourceLab DSLogic Pro (after FW upload) */
 	{ 0x2a0e, 0x0003, "DreamSourceLab", "DSLogic Pro", NULL,
 		"dreamsourcelab-dslogic-pro-fx2.fw",
-		DEV_CAPS_16BIT, "DreamSourceLab", "DSLogic"},
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", "DSLogic"},
+
+	/* DreamSourceLab DSLogic Plus (before FW upload) */
+	{ 0x2a0e, 0x0020, "DreamSourceLab", "DSLogic Plus", NULL,
+		"dreamsourcelab-dslogic-plus-fx2.fw",
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
+	/* DreamSourceLab DSLogic Plus (after FW upload) */
+	{ 0x2a0e, 0x0020, "DreamSourceLab", "DSLogic Plus", NULL,
+		"dreamsourcelab-dslogic-plus-fx2.fw",
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", "DSLogic"},
+
+	/* DreamSourceLab DSLogic Basic (before FW upload) */
+	{ 0x2a0e, 0x0021, "DreamSourceLab", "DSLogic Basic", NULL,
+		"dreamsourcelab-dslogic-basic-fx2.fw",
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, NULL, NULL},
+	/* DreamSourceLab DSLogic Basic (after FW upload) */
+	{ 0x2a0e, 0x0021, "DreamSourceLab", "DSLogic Basic", NULL,
+		"dreamsourcelab-dslogic-basic-fx2.fw",
+		DEV_CAPS_16BIT | DEV_CAPS_DSLOGIC_FW, "DreamSourceLab", "DSLogic"},
 
 	/*
 	 * Saleae Logic
@@ -388,6 +406,8 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 
 		if (!strcmp(prof->model, "DSLogic")
 				|| !strcmp(prof->model, "DSLogic Pro")
+				|| !strcmp(prof->model, "DSLogic Plus")
+				|| !strcmp(prof->model, "DSLogic Basic")
 				|| !strcmp(prof->model, "DSCope")) {
 			devc->dslogic = TRUE;
 			devc->samplerates = dslogic_samplerates;
@@ -517,6 +537,10 @@ static int dev_open(struct sr_dev_inst *sdi)
 				fpga_firmware = DSLOGIC_FPGA_FIRMWARE_5V;
 		} else if (!strcmp(devc->profile->model, "DSLogic Pro")){
 			fpga_firmware = DSLOGIC_PRO_FPGA_FIRMWARE;
+		} else if (!strcmp(devc->profile->model, "DSLogic Plus")){
+			fpga_firmware = DSLOGIC_PLUS_FPGA_FIRMWARE;
+		} else if (!strcmp(devc->profile->model, "DSLogic Basic")){
+			fpga_firmware = DSLOGIC_BASIC_FPGA_FIRMWARE;
 		} else if (!strcmp(devc->profile->model, "DSCope")) {
 			fpga_firmware = DSCOPE_FPGA_FIRMWARE;
 		}
@@ -695,6 +719,10 @@ static int config_set(uint32_t key, GVariant *data,
 				ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3);
 		} else if (!strcmp(devc->profile->model, "DSLogic Pro")) {
 			ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE);
+		} else if (!strcmp(devc->profile->model, "DSLogic Plus")) {
+			ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PLUS_FPGA_FIRMWARE);
+		} else if (!strcmp(devc->profile->model, "DSLogic Basic")) {
+			ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_BASIC_FPGA_FIRMWARE);
 		}
 		break;
 	case SR_CONF_EXTERNAL_CLOCK:
@@ -709,7 +737,7 @@ static int config_set(uint32_t key, GVariant *data,
 		if (i < 0)
 			return SR_ERR_ARG;
 		devc->dslogic_clock_edge = i;
-		break;		
+		break;
 	default:
 		ret = SR_ERR_NA;
 	}
@@ -1004,10 +1032,13 @@ static int configure_channels(const struct sr_dev_inst *sdi)
 	}
 
 	/*
-	 * Use wide sampling if either any of the LA channels 8..15 is enabled
-	 * and/or at least one analog channel is enabled.
+	 * Use wide sampling if either any of the LA channels 8..15 is enabled,
+	 * and/or at least one analog channel is enabled, and/or the device
+	 * is running DSLogic firmware (not fx2lafw).
 	 */
-	devc->sample_wide = (channel_mask > 0xff || num_analog > 0);
+	devc->sample_wide = (channel_mask > 0xff
+			|| num_analog > 0
+			|| (devc->profile->dev_caps & DEV_CAPS_DSLOGIC_FW));
 
 	return SR_OK;
 }