X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Ffx2lafw%2Fapi.c;h=17ae297c9f3f37544c7d659ec1757c5eaad5361c;hb=d9a58763d66b761900fdc930d9cd580137ea3a5c;hp=6f6c53fb09c215b68e3f7370aa7c99d47c25e145;hpb=c45c32ce47f429099cb0f1cabc1b45b9bcf44855;p=libsigrok.git diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c index 6f6c53fb..17ae297c 100644 --- a/src/hardware/fx2lafw/api.c +++ b/src/hardware/fx2lafw/api.c @@ -21,6 +21,7 @@ #include #include "protocol.h" #include "dslogic.h" +#include static const struct fx2lafw_profile supported_fx2[] = { /* @@ -133,6 +134,18 @@ static const uint32_t devopts[] = { SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, }; +static const uint32_t dslogic_devopts[] = { + SR_CONF_CONTINUOUS | SR_CONF_SET | SR_CONF_GET, + SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, + SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, + SR_CONF_CONN | SR_CONF_GET, + SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, + SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, + SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, + SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, + SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST +}; + static const int32_t soft_trigger_matches[] = { SR_TRIGGER_ZERO, SR_TRIGGER_ONE, @@ -141,6 +154,22 @@ static const int32_t soft_trigger_matches[] = { SR_TRIGGER_EDGE, }; +/* Names assigned to available edge slope choices. + */ +static const char *const signal_edge_names[] = { + [DS_EDGE_RISING] = "rising", + [DS_EDGE_FALLING] = "falling", +}; + +static const struct { + int range; + gdouble low; + gdouble high; +} volt_thresholds[] = { + { DS_VOLTAGE_RANGE_18_33_V, 0.7, 1.4 }, + { DS_VOLTAGE_RANGE_5_V, 1.4, 3.6 }, +}; + static const uint64_t samplerates[] = { SR_KHZ(20), SR_KHZ(25), @@ -181,11 +210,6 @@ static const uint64_t dslogic_samplerates[] = { SR_PRIV struct sr_dev_driver fx2lafw_driver_info; -static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx) -{ - return std_init(di, sr_ctx); -} - static GSList *scan(struct sr_dev_driver *di, GSList *options) { struct drv_context *drvc; @@ -466,18 +490,19 @@ static int dev_open(struct sr_dev_inst *sdi) if (devc->dslogic) { if (!strcmp(devc->profile->model, "DSLogic")) { - fpga_firmware = DSLOGIC_FPGA_FIRMWARE; - } else if (!strcmp(devc->profile->model, "DSLogic Pro")) { + if (devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V) + fpga_firmware = DSLOGIC_FPGA_FIRMWARE_3V3; + else + fpga_firmware = DSLOGIC_FPGA_FIRMWARE_5V; + } else if (!strcmp(devc->profile->model, "DSLogic Pro")){ fpga_firmware = DSLOGIC_PRO_FPGA_FIRMWARE; } else if (!strcmp(devc->profile->model, "DSCope")) { fpga_firmware = DSCOPE_FPGA_FIRMWARE; } - if ((ret = dslogic_fpga_firmware_upload(sdi, - fpga_firmware)) != SR_OK) + if ((ret = dslogic_fpga_firmware_upload(sdi, fpga_firmware)) != SR_OK) return ret; } - if (devc->cur_samplerate == 0) { /* Samplerate hasn't been set; default to the slowest one. */ devc->cur_samplerate = devc->samplerates[0]; @@ -509,6 +534,8 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s { struct dev_context *devc; struct sr_usb_dev_inst *usb; + GVariant *range[2]; + unsigned int i; char str[128]; (void)cg; @@ -530,6 +557,16 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s snprintf(str, 128, "%d.%d", usb->bus, usb->address); *data = g_variant_new_string(str); break; + case SR_CONF_VOLTAGE_THRESHOLD: + for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) { + if (volt_thresholds[i].range != devc->dslogic_voltage_threshold) + continue; + range[0] = g_variant_new_double(volt_thresholds[i].low); + range[1] = g_variant_new_double(volt_thresholds[i].high); + *data = g_variant_new_tuple(range, 2); + break; + } + break; case SR_CONF_LIMIT_SAMPLES: *data = g_variant_new_uint64(devc->limit_samples); break; @@ -539,6 +576,18 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s case SR_CONF_CAPTURE_RATIO: *data = g_variant_new_uint64(devc->capture_ratio); break; + case SR_CONF_EXTERNAL_CLOCK: + *data = g_variant_new_boolean(devc->dslogic_external_clock); + break; + case SR_CONF_CONTINUOUS: + *data = g_variant_new_boolean(devc->dslogic_continuous_mode); + break; + case SR_CONF_CLOCK_EDGE: + i = devc->dslogic_clock_edge; + if (i >= ARRAY_SIZE(signal_edge_names)) + return SR_ERR_BUG; + *data = g_variant_new_string(signal_edge_names[0]);//idx]); + break; default: return SR_ERR_NA; } @@ -546,12 +595,35 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s return SR_OK; } + +/* Helper for mapping a string-typed configuration value to an index + * within a table of possible values. + */ +static int lookup_index(GVariant *value, const char *const *table, int len) +{ + const char *entry; + int i; + + entry = g_variant_get_string(value, NULL); + if (!entry) + return -1; + + /* Linear search is fine for very small tables. */ + for (i = 0; i < len; i++) { + if (strcmp(entry, table[i]) == 0) + return i; + } + + return -1; +} + static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) { struct dev_context *devc; uint64_t arg; int i, ret; + gdouble low, high; (void)cg; @@ -584,6 +656,38 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd devc->capture_ratio = g_variant_get_uint64(data); ret = (devc->capture_ratio > 100) ? SR_ERR : SR_OK; break; + case SR_CONF_VOLTAGE_THRESHOLD: + g_variant_get(data, "(dd)", &low, &high); + ret = SR_ERR_ARG; + for (i = 0; (unsigned int)i < ARRAY_SIZE(volt_thresholds); i++) { + if (fabs(volt_thresholds[i].low - low) < 0.1 && + fabs(volt_thresholds[i].high - high) < 0.1) { + devc->dslogic_voltage_threshold = volt_thresholds[i].range; + break; + } + } + if (!strcmp(devc->profile->model, "DSLogic")) { + if (devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_5_V) + ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_5V); + else + ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_FPGA_FIRMWARE_3V3); + }else if (!strcmp(devc->profile->model, "DSLogic Pro")){ + ret = dslogic_fpga_firmware_upload(sdi, DSLOGIC_PRO_FPGA_FIRMWARE); + } + break; + case SR_CONF_EXTERNAL_CLOCK: + devc->dslogic_external_clock = g_variant_get_boolean(data); + break; + case SR_CONF_CONTINUOUS: + devc->dslogic_continuous_mode = g_variant_get_boolean(data); + break; + case SR_CONF_CLOCK_EDGE: + i = lookup_index(data, signal_edge_names, + ARRAY_SIZE(signal_edge_names)); + if (i < 0) + return SR_ERR_ARG; + devc->dslogic_clock_edge = i; + break; default: ret = SR_ERR_NA; } @@ -595,8 +699,9 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst * const struct sr_channel_group *cg) { struct dev_context *devc; - GVariant *gvar; + GVariant *gvar, *range[2]; GVariantBuilder gvb; + unsigned int i; (void)cg; @@ -608,10 +713,29 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst * case SR_CONF_DEVICE_OPTIONS: if (!sdi) *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, - drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t)); - else - *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, - devopts, ARRAY_SIZE(devopts), sizeof(uint32_t)); + drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t)); + else{ + devc = sdi->priv; + if (!devc->dslogic) + *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, + devopts, ARRAY_SIZE(devopts), sizeof(uint32_t)); + else + *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32, + dslogic_devopts, ARRAY_SIZE(dslogic_devopts), sizeof(uint32_t)); + } + break; + case SR_CONF_VOLTAGE_THRESHOLD: + if (!sdi->priv) return SR_ERR_ARG; + devc = sdi->priv; + if (!devc->dslogic) return SR_ERR_NA; + g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY); + for (i = 0; i < ARRAY_SIZE(volt_thresholds); i++) { + range[0] = g_variant_new_double(volt_thresholds[i].low); + range[1] = g_variant_new_double(volt_thresholds[i].high); + gvar = g_variant_new_tuple(range, 2); + g_variant_builder_add_value(&gvb, gvar); + } + *data = g_variant_builder_end(&gvb); break; case SR_CONF_SAMPLERATE: if (!sdi->priv) @@ -628,6 +752,10 @@ static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst * soft_trigger_matches, ARRAY_SIZE(soft_trigger_matches), sizeof(int32_t)); break; + case SR_CONF_CLOCK_EDGE: + *data = g_variant_new_strv(signal_edge_names, + ARRAY_SIZE(signal_edge_names)); + break; default: return SR_ERR_NA; } @@ -669,7 +797,7 @@ static int start_transfers(const struct sr_dev_inst *sdi) devc->acq_aborted = FALSE; devc->empty_transfer_count = 0; - if ((trigger = sr_session_trigger_get(sdi->session))) { + if ((trigger = sr_session_trigger_get(sdi->session)) && !devc->dslogic) { int pre_trigger_samples = 0; if (devc->limit_samples > 0) pre_trigger_samples = devc->capture_ratio * devc->limit_samples/100; @@ -746,11 +874,11 @@ static void LIBUSB_CALL dslogic_trigger_receive(struct libusb_transfer *transfer } else if (transfer->status == LIBUSB_TRANSFER_COMPLETED && transfer->actual_length == sizeof(struct dslogic_trigger_pos)) { tpos = (struct dslogic_trigger_pos *)transfer->buffer; - sr_dbg("tpos real_pos %.8x ram_saddr %.8x", tpos->real_pos, tpos->ram_saddr); + sr_info("tpos real_pos %d ram_saddr %d cnt %d", tpos->real_pos, tpos->ram_saddr, tpos->remain_cnt); + devc->trigger_pos = tpos->real_pos; g_free(tpos); start_transfers(sdi); } - libusb_free_transfer(transfer); } @@ -771,6 +899,15 @@ static int dslogic_trigger_request(const struct sr_dev_inst *sdi) if ((ret = dslogic_fpga_configure(sdi)) != SR_OK) return ret; + /* if this is a dslogic pro, set the voltage threshold */ + if (!strcmp(devc->profile->model, "DSLogic Pro")){ + if(devc->dslogic_voltage_threshold == DS_VOLTAGE_RANGE_18_33_V){ + dslogic_set_vth(sdi, 1.4); + }else{ + dslogic_set_vth(sdi, 3.3); + } + } + if ((ret = dslogic_start_acquisition(sdi)) != SR_OK) return ret; @@ -891,7 +1028,7 @@ SR_PRIV struct sr_dev_driver fx2lafw_driver_info = { .name = "fx2lafw", .longname = "fx2lafw (generic driver for FX2 based LAs)", .api_version = 1, - .init = init, + .init = std_init, .cleanup = std_cleanup, .scan = scan, .dev_list = std_dev_list,