X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fdreamsourcelab-dslogic%2Fprotocol.c;h=90b773d9cf970fe34d48193cea23de0792d046f5;hb=6c1a4cb44ccd24b2b23477c86273a8e405758c03;hp=2bf3366824434f09394c34f4e5976d5c6092ea75;hpb=16d4c982a341ecc4118b5cbdbb26ef5df93ae31b;p=libsigrok.git

diff --git a/src/hardware/dreamsourcelab-dslogic/protocol.c b/src/hardware/dreamsourcelab-dslogic/protocol.c
index 2bf33668..90b773d9 100644
--- a/src/hardware/dreamsourcelab-dslogic/protocol.c
+++ b/src/hardware/dreamsourcelab-dslogic/protocol.c
@@ -20,6 +20,7 @@
 
 #include <config.h>
 #include <math.h>
+#include <stdbool.h>
 #include <glib.h>
 #include <glib/gstdio.h>
 #include "protocol.h"
@@ -336,8 +337,9 @@ static uint16_t enabled_channel_mask(const struct sr_dev_inst *sdi)
 /*
  * Get the session trigger and configure the FPGA structure
  * accordingly.
+ * @return @c true if any triggers are enabled, @c false otherwise.
  */
-static void set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
+static bool set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
 {
 	struct sr_trigger *trigger;
 	struct sr_trigger_stage *stage;
@@ -378,7 +380,7 @@ static void set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
 
 	if (!(trigger = sr_session_trigger_get(sdi->session))) {
 		sr_dbg("No session trigger found");
-		return;
+		return false;
 	}
 
 	for (l = trigger->stages; l; l = l->next) {
@@ -419,6 +421,8 @@ static void set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
 	}
 
 	cfg->trig_glb = (num_enabled_channels << 4) | (num_trigger_stages - 1);
+
+	return num_trigger_stages != 0;
 }
 
 static int fpga_configure(const struct sr_dev_inst *sdi)
@@ -458,12 +462,15 @@ static int fpga_configure(const struct sr_dev_inst *sdi)
 		return SR_ERR;
 	}
 
+	if (set_trigger(sdi, &cfg))
+		mode |= DS_MODE_TRIG_EN;
+
 	if (devc->mode == DS_OP_INTERNAL_TEST)
-		mode = DS_MODE_INT_TEST;
+		mode |= DS_MODE_INT_TEST;
 	else if (devc->mode == DS_OP_EXTERNAL_TEST)
-		mode = DS_MODE_EXT_TEST;
+		mode |= DS_MODE_EXT_TEST;
 	else if (devc->mode == DS_OP_LOOPBACK_TEST)
-		mode = DS_MODE_LPB_TEST;
+		mode |= DS_MODE_LPB_TEST;
 
 	if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
 		mode |= DS_MODE_HALF_MODE;
@@ -493,8 +500,6 @@ static int fpga_configure(const struct sr_dev_inst *sdi)
 	/* Number of 16-sample units. */
 	WL32(&cfg.count, devc->limit_samples / 16);
 
-	set_trigger(sdi, &cfg);
-
 	len = sizeof(struct fpga_config);
 	ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
 			(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
@@ -728,10 +733,12 @@ static void deinterleave_buffer(const uint8_t *src, size_t length,
 		for (int bit = 0; bit != 64; bit++) {
 			const uint64_t *word_ptr = src_ptr;
 			sample = 0;
-			for (size_t channel = 0; channel != channel_count;
+			for (unsigned int channel = 0; channel != 16;
 				channel++) {
-				if ((channel_mask & (1 << channel)) &&
-					(*word_ptr++ & (1ULL << bit)))
+				const uint16_t m = channel_mask >> channel;
+				if (!m)
+					break;
+				if ((m & 1) && ((*word_ptr++ >> bit) & 1ULL))
 					sample |= 1 << channel;
 			}
 			*dst_ptr++ = sample;