X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fdreamsourcelab-dslogic%2Fapi.c;h=f7dd72565e608967a81465c59f7cd404ad7347af;hb=b3fd09937ce099d5a7086ff6bbdfa1b4f371cabd;hp=4e0a1d10016eddff95be28ad75e3f12817dbe5cd;hpb=758906aa711c2936e7e9adcb449f70905087a5d9;p=libsigrok.git

diff --git a/src/hardware/dreamsourcelab-dslogic/api.c b/src/hardware/dreamsourcelab-dslogic/api.c
index 4e0a1d10..f7dd7256 100644
--- a/src/hardware/dreamsourcelab-dslogic/api.c
+++ b/src/hardware/dreamsourcelab-dslogic/api.c
@@ -67,12 +67,12 @@ static const uint32_t devopts[] = {
 	SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 };
 
-static const char *signal_edge_names[] = {
+static const char *signal_edges[] = {
 	[DS_EDGE_RISING] = "rising",
 	[DS_EDGE_FALLING] = "falling",
 };
 
-static const double voltage_thresholds[][2] = {
+static const double thresholds[][2] = {
 	{ 0.7, 1.4 },
 	{ 1.4, 3.6 },
 };
@@ -233,7 +233,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 		/* Logic channels, all in one channel group. */
 		cg = g_malloc0(sizeof(struct sr_channel_group));
 		cg->name = g_strdup("Logic");
-		for (j = 0; j < 16; j++) {
+		for (j = 0; j < NUM_CHANNELS; j++) {
 			sprintf(channel_name, "%d", j);
 			ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
 						TRUE, channel_name);
@@ -403,10 +403,10 @@ static int config_get(uint32_t key, GVariant **data,
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic")) {
 			if ((idx = std_double_tuple_idx_d0(devc->cur_threshold,
-					ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+					ARRAY_AND_SIZE(thresholds))) < 0)
 				return SR_ERR_BUG;
-			*data = std_gvar_tuple_double(voltage_thresholds[idx][0],
-					voltage_thresholds[idx][1]);
+			*data = std_gvar_tuple_double(thresholds[idx][0],
+					thresholds[idx][1]);
 		} else {
 			*data = std_gvar_tuple_double(devc->cur_threshold, devc->cur_threshold);
 		}
@@ -428,9 +428,9 @@ static int config_get(uint32_t key, GVariant **data,
 		break;
 	case SR_CONF_CLOCK_EDGE:
 		idx = devc->clock_edge;
-		if (idx >= (int)ARRAY_SIZE(signal_edge_names))
+		if (idx >= (int)ARRAY_SIZE(signal_edges))
 			return SR_ERR_BUG;
-		*data = g_variant_new_string(signal_edge_names[0]);
+		*data = g_variant_new_string(signal_edges[0]);
 		break;
 	default:
 		return SR_ERR_NA;
@@ -464,12 +464,12 @@ static int config_set(uint32_t key, GVariant *data,
 		break;
 	case SR_CONF_CAPTURE_RATIO:
 		devc->capture_ratio = g_variant_get_uint64(data);
-		return (devc->capture_ratio > 100) ? SR_ERR : SR_OK;
+		break;
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic")) {
-			if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+			if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(thresholds))) < 0)
 				return SR_ERR_ARG;
-			devc->cur_threshold = voltage_thresholds[idx][0];
+			devc->cur_threshold = thresholds[idx][0];
 			return dslogic_fpga_firmware_upload(sdi);
 		} else {
 			g_variant_get(data, "(dd)", &low, &high);
@@ -483,7 +483,7 @@ static int config_set(uint32_t key, GVariant *data,
 		devc->continuous_mode = g_variant_get_boolean(data);
 		break;
 	case SR_CONF_CLOCK_EDGE:
-		if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edge_names))) < 0)
+		if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
 			return SR_ERR_ARG;
 		devc->clock_edge = idx;
 		break;
@@ -507,7 +507,7 @@ static int config_list(uint32_t key, GVariant **data,
 		return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic"))
-			*data = std_gvar_thresholds(ARRAY_AND_SIZE(voltage_thresholds));
+			*data = std_gvar_thresholds(ARRAY_AND_SIZE(thresholds));
 		else
 			*data = std_gvar_min_max_step_thresholds(0.0, 5.0, 0.1);
 		break;
@@ -515,7 +515,7 @@ static int config_list(uint32_t key, GVariant **data,
 		*data = std_gvar_samplerates(devc->samplerates, devc->num_samplerates);
 		break;
 	case SR_CONF_CLOCK_EDGE:
-		*data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edge_names));
+		*data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
 		break;
 	default:
 		return SR_ERR_NA;