X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fdreamsourcelab-dslogic%2Fapi.c;h=66c810372efd583880697b1724820cff39ea1b15;hb=d8fb599c679a6da64f28bcafce514558b786b6c7;hp=294e5d16ed7bc36755043cbd031d78dad64bf385;hpb=e124cf9b7aff90bfa6bc1a0028744c29c7211388;p=libsigrok.git

diff --git a/src/hardware/dreamsourcelab-dslogic/api.c b/src/hardware/dreamsourcelab-dslogic/api.c
index 294e5d16..66c81037 100644
--- a/src/hardware/dreamsourcelab-dslogic/api.c
+++ b/src/hardware/dreamsourcelab-dslogic/api.c
@@ -67,12 +67,20 @@ static const uint32_t devopts[] = {
 	SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 };
 
+static const int32_t trigger_matches[] = {
+	SR_TRIGGER_ZERO,
+	SR_TRIGGER_ONE,
+	SR_TRIGGER_RISING,
+	SR_TRIGGER_FALLING,
+	SR_TRIGGER_EDGE,
+};
+
 static const char *signal_edges[] = {
 	[DS_EDGE_RISING] = "rising",
 	[DS_EDGE_FALLING] = "falling",
 };
 
-static const double voltage_thresholds[][2] = {
+static const double thresholds[][2] = {
 	{ 0.7, 1.4 },
 	{ 1.4, 3.6 },
 };
@@ -233,7 +241,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
 		/* Logic channels, all in one channel group. */
 		cg = g_malloc0(sizeof(struct sr_channel_group));
 		cg->name = g_strdup("Logic");
-		for (j = 0; j < 16; j++) {
+		for (j = 0; j < NUM_CHANNELS; j++) {
 			sprintf(channel_name, "%d", j);
 			ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
 						TRUE, channel_name);
@@ -352,7 +360,7 @@ static int dev_open(struct sr_dev_inst *sdi)
 	}
 
 	if (devc->cur_threshold == 0.0)
-		devc->cur_threshold = 1.5;
+		devc->cur_threshold = thresholds[1][0];
 
 	return SR_OK;
 }
@@ -403,10 +411,10 @@ static int config_get(uint32_t key, GVariant **data,
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic")) {
 			if ((idx = std_double_tuple_idx_d0(devc->cur_threshold,
-					ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+					ARRAY_AND_SIZE(thresholds))) < 0)
 				return SR_ERR_BUG;
-			*data = std_gvar_tuple_double(voltage_thresholds[idx][0],
-					voltage_thresholds[idx][1]);
+			*data = std_gvar_tuple_double(thresholds[idx][0],
+					thresholds[idx][1]);
 		} else {
 			*data = std_gvar_tuple_double(devc->cur_threshold, devc->cur_threshold);
 		}
@@ -467,9 +475,9 @@ static int config_set(uint32_t key, GVariant *data,
 		break;
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic")) {
-			if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+			if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(thresholds))) < 0)
 				return SR_ERR_ARG;
-			devc->cur_threshold = voltage_thresholds[idx][0];
+			devc->cur_threshold = thresholds[idx][0];
 			return dslogic_fpga_firmware_upload(sdi);
 		} else {
 			g_variant_get(data, "(dd)", &low, &high);
@@ -507,13 +515,16 @@ static int config_list(uint32_t key, GVariant **data,
 		return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
 	case SR_CONF_VOLTAGE_THRESHOLD:
 		if (!strcmp(devc->profile->model, "DSLogic"))
-			*data = std_gvar_thresholds(ARRAY_AND_SIZE(voltage_thresholds));
+			*data = std_gvar_thresholds(ARRAY_AND_SIZE(thresholds));
 		else
 			*data = std_gvar_min_max_step_thresholds(0.0, 5.0, 0.1);
 		break;
 	case SR_CONF_SAMPLERATE:
 		*data = std_gvar_samplerates(devc->samplerates, devc->num_samplerates);
 		break;
+	case SR_CONF_TRIGGER_MATCH:
+		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
+		break;
 	case SR_CONF_CLOCK_EDGE:
 		*data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
 		break;