X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.c;h=f9e54089cb5ef270f5bda887339fe53686c74c87;hb=2c33b092553c4116151aeb59f129f2f0a598741e;hp=b23b26ff832cca1cb4d0d8aa1d938c1631512bf2;hpb=4154a516de818ace3aabfe5e44cf4c81986074e7;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c index b23b26ff..f9e54089 100644 --- a/src/hardware/asix-sigma/protocol.c +++ b/src/hardware/asix-sigma/protocol.c @@ -26,12 +26,6 @@ #include #include "protocol.h" -#define USB_VENDOR 0xa600 -#define USB_PRODUCT 0xa000 -#define USB_DESCRIPTION "ASIX SIGMA" -#define USB_VENDOR_NAME "ASIX" -#define USB_MODEL_NAME "SIGMA" - /* * The ASIX Sigma supports arbitrary integer frequency divider in * the 50MHz mode. The divider is in range 1...256 , allowing for @@ -53,19 +47,16 @@ SR_PRIV const uint64_t samplerates[] = { SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates); -static const char sigma_firmware_files[][24] = { - /* 50 MHz, supports 8 bit fractions */ - "asix-sigma-50.fw", - /* 100 MHz */ - "asix-sigma-100.fw", - /* 200 MHz */ - "asix-sigma-200.fw", - /* Synchronous clock from pin */ - "asix-sigma-50sync.fw", - /* Frequency counter */ - "asix-sigma-phasor.fw", +static const char *firmware_files[] = { + "asix-sigma-50.fw", /* Up to 50MHz sample rate, 8bit divider. */ + "asix-sigma-100.fw", /* 100MHz sample rate, fixed. */ + "asix-sigma-200.fw", /* 200MHz sample rate, fixed. */ + "asix-sigma-50sync.fw", /* Synchronous clock from external pin. */ + "asix-sigma-phasor.fw", /* Frequency counter. */ }; +#define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024) + static int sigma_read(void *buf, size_t size, struct dev_context *devc) { int ret; @@ -84,12 +75,11 @@ static int sigma_write(void *buf, size_t size, struct dev_context *devc) int ret; ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); - if (ret < 0) { + if (ret < 0) sr_err("ftdi_write_data failed: %s", ftdi_get_error_string(&devc->ftdic)); - } else if ((size_t) ret != size) { + else if ((size_t) ret != size) sr_err("ftdi_write_data did not complete write."); - } return ret; } @@ -105,9 +95,9 @@ SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, uint8_t buf[80]; int idx = 0; - if ((len + 2) > sizeof(buf)) { + if ((2 * len + 2) > sizeof(buf)) { sr_err("Attempted to write %zu bytes, but buffer is too small.", - len + 2); + len); return SR_ERR_BUG; } @@ -141,30 +131,21 @@ static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, return sigma_read(data, len, devc); } -static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) -{ - uint8_t value; - - if (1 != sigma_read_register(reg, &value, 1, devc)) { - sr_err("sigma_get_register: 1 byte expected"); - return 0; - } - - return value; -} - static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, struct dev_context *devc) { + /* + * Read 6 registers starting at trigger position LSB. + * Which yields two 24bit counter values. + */ uint8_t buf[] = { REG_ADDR_LOW | READ_TRIGGER_POS_LOW, - - REG_READ_ADDR | NEXT_REG, - REG_READ_ADDR | NEXT_REG, - REG_READ_ADDR | NEXT_REG, - REG_READ_ADDR | NEXT_REG, - REG_READ_ADDR | NEXT_REG, - REG_READ_ADDR | NEXT_REG, + REG_READ_ADDR | REG_ADDR_INC, + REG_READ_ADDR | REG_ADDR_INC, + REG_READ_ADDR | REG_ADDR_INC, + REG_READ_ADDR | REG_ADDR_INC, + REG_READ_ADDR | REG_ADDR_INC, + REG_READ_ADDR | REG_ADDR_INC, }; uint8_t result[6]; @@ -175,11 +156,25 @@ static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); - /* Not really sure why this must be done, but according to spec. */ + /* + * These "position" values point to after the event (end of + * capture data, trigger condition matched). This is why they + * get decremented here. Sample memory consists of 512-byte + * chunks with meta data in the upper 64 bytes. Thus when the + * decrements takes us into this upper part of the chunk, then + * further move backwards to the end of the chunk's data part. + * + * TODO Re-consider the above comment's validity. It's true + * that a 1024byte row contains 512 u16 entities, of which 64 + * are timestamps and 448 are events with sample data. It's not + * true that 64bytes of metadata reside at the top of a 512byte + * block in a row. + * + * TODO Use ROW_MASK and CLUSTERS_PER_ROW here? + */ if ((--*stoppos & 0x1ff) == 0x1ff) *stoppos -= 64; - - if ((*--triggerpos & 0x1ff) == 0x1ff) + if ((--*triggerpos & 0x1ff) == 0x1ff) *triggerpos -= 64; return 1; @@ -188,33 +183,38 @@ static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data, struct dev_context *devc) { - size_t i; uint8_t buf[4096]; - int idx = 0; + int idx; + size_t chunk; + int sel; + gboolean is_last; - /* Send the startchunk. Index start with 1. */ - buf[0] = startchunk >> 8; - buf[1] = startchunk & 0xff; - sigma_write_register(WRITE_MEMROW, buf, 2, devc); + /* Communicate DRAM start address (memory row, aka samples line). */ + idx = 0; + buf[idx++] = startchunk >> 8; + buf[idx++] = startchunk & 0xff; + sigma_write_register(WRITE_MEMROW, buf, idx, devc); - /* Read the DRAM. */ + /* + * Access DRAM content. Fetch from DRAM to FPGA's internal RAM, + * then transfer via USB. Interleave the FPGA's DRAM access and + * USB transfer, use alternating buffers (0/1) in the process. + */ + idx = 0; buf[idx++] = REG_DRAM_BLOCK; buf[idx++] = REG_DRAM_WAIT_ACK; - - for (i = 0; i < numchunks; i++) { - /* Alternate bit to copy from DRAM to cache. */ - if (i != (numchunks - 1)) - buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); - - buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); - - if (i != (numchunks - 1)) + for (chunk = 0; chunk < numchunks; chunk++) { + sel = chunk % 2; + is_last = chunk == numchunks - 1; + if (!is_last) + buf[idx++] = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel); + buf[idx++] = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel); + if (!is_last) buf[idx++] = REG_DRAM_WAIT_ACK; } - sigma_write(buf, idx, devc); - return sigma_read(data, numchunks * CHUNK_SIZE, devc); + return sigma_read(data, numchunks * ROW_LENGTH_BYTES, devc); } /* Upload trigger look-up tables to Sigma. */ @@ -264,43 +264,83 @@ SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context * if (lut->m1d[3] & bit) tmp[1] |= 0x80; - sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), + sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp), devc); - sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); + sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc); } /* Send the parameters */ - sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, + sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params, sizeof(lut->params), devc); return SR_OK; } -SR_PRIV void sigma_clear_helper(void *priv) -{ - struct dev_context *devc; - - devc = priv; - - ftdi_deinit(&devc->ftdic); -} +/* + * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device + * uses FTDI bitbang mode for netlist download in slave serial mode. + * (LATER: The OMEGA device's cable contains a more capable FTDI chip + * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245 + * compatible bitbang mode? For maximum code re-use and reduced libftdi + * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2 + * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.) + * + * 750kbps rate (four times the speed of sigmalogan) works well for + * netlist download. All pins except INIT_B are output pins during + * configuration download. + * + * Some pins are inverted as a byproduct of level shifting circuitry. + * That's why high CCLK level (from the cable's point of view) is idle + * from the FPGA's perspective. + * + * The vendor's literature discusses a "suicide sequence" which ends + * regular FPGA execution and should be sent before entering bitbang + * mode and sending configuration data. Set D7 and toggle D2, D3, D4 + * a few times. + */ +#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ +#define BB_PIN_PROG (1 << 1) /* D1, PROG */ +#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ +#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ +#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ +#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ +#define BB_PIN_DIN (1 << 6) /* D6, DIN */ +#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ + +#define BB_BITRATE (750 * 1000) +#define BB_PINMASK (0xff & ~BB_PIN_INIT) /* - * Configure the FPGA for bitbang mode. - * This sequence is documented in section 2. of the ASIX Sigma programming - * manual. This sequence is necessary to configure the FPGA in the Sigma - * into Bitbang mode, in which it can be programmed with the firmware. + * Initiate slave serial mode for configuration download. Which is done + * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before + * initiating the configuration download. Run a "suicide sequence" first + * to terminate the regular FPGA operation before reconfiguration. */ static int sigma_fpga_init_bitbang(struct dev_context *devc) { uint8_t suicide[] = { - 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, + BB_PIN_D7 | BB_PIN_D2, + BB_PIN_D7 | BB_PIN_D2, + BB_PIN_D7 | BB_PIN_D3, + BB_PIN_D7 | BB_PIN_D2, + BB_PIN_D7 | BB_PIN_D3, + BB_PIN_D7 | BB_PIN_D2, + BB_PIN_D7 | BB_PIN_D3, + BB_PIN_D7 | BB_PIN_D2, }; uint8_t init_array[] = { - 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, + BB_PIN_CCLK, + BB_PIN_CCLK | BB_PIN_PROG, + BB_PIN_CCLK | BB_PIN_PROG, + BB_PIN_CCLK, + BB_PIN_CCLK, + BB_PIN_CCLK, + BB_PIN_CCLK, + BB_PIN_CCLK, + BB_PIN_CCLK, + BB_PIN_CCLK, }; - int i, ret, timeout = (10 * 1000); + int retries, ret; uint8_t data; /* Section 2. part 1), do the FPGA suicide. */ @@ -309,19 +349,18 @@ static int sigma_fpga_init_bitbang(struct dev_context *devc) sigma_write(suicide, sizeof(suicide), devc); sigma_write(suicide, sizeof(suicide), devc); - /* Section 2. part 2), do pulse on D1. */ + /* Section 2. part 2), pulse PROG. */ sigma_write(init_array, sizeof(init_array), devc); ftdi_usb_purge_buffers(&devc->ftdic); - /* Wait until the FPGA asserts D6/INIT_B. */ - for (i = 0; i < timeout; i++) { + /* Wait until the FPGA asserts INIT_B. */ + retries = 10; + while (retries--) { ret = sigma_read(&data, 1, devc); if (ret < 0) return ret; - /* Test if pin D6 got asserted. */ - if (data & (1 << 5)) - return 0; - /* The D6 was not asserted yet, wait a bit. */ + if (data & BB_PIN_INIT) + return SR_OK; g_usleep(10 * 1000); } @@ -333,41 +372,49 @@ static int sigma_fpga_init_bitbang(struct dev_context *devc) */ static int sigma_fpga_init_la(struct dev_context *devc) { - /* Initialize the logic analyzer mode. */ + /* + * TODO Construct the sequence at runtime? Such that request data + * and response check values will match more apparently? + */ + uint8_t mode_regval = WMR_SDRAMINIT; uint8_t logic_mode_start[] = { + /* Read ID register. */ REG_ADDR_LOW | (READ_ID & 0xf), - REG_ADDR_HIGH | (READ_ID >> 8), - REG_READ_ADDR, /* Read ID register. */ + REG_ADDR_HIGH | (READ_ID >> 4), + REG_READ_ADDR, + /* Write 0x55 to scratch register, read back. */ REG_ADDR_LOW | (WRITE_TEST & 0xf), REG_DATA_LOW | 0x5, REG_DATA_HIGH_WRITE | 0x5, - REG_READ_ADDR, /* Read scratch register. */ + REG_READ_ADDR, + /* Write 0xaa to scratch register, read back. */ REG_DATA_LOW | 0xa, REG_DATA_HIGH_WRITE | 0xa, - REG_READ_ADDR, /* Read scratch register. */ + REG_READ_ADDR, + /* Initiate SDRAM initialization in mode register. */ REG_ADDR_LOW | (WRITE_MODE & 0xf), - REG_DATA_LOW | 0x0, - REG_DATA_HIGH_WRITE | 0x8, + REG_DATA_LOW | (mode_regval & 0xf), + REG_DATA_HIGH_WRITE | (mode_regval >> 4), }; - uint8_t result[3]; int ret; - /* Initialize the logic analyzer mode. */ + /* + * Send the command sequence which contains 3 READ requests. + * Expect to see the corresponding 3 response bytes. + */ sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); - - /* Expect a 3 byte reply since we issued three READ requests. */ - ret = sigma_read(result, 3, devc); - if (ret != 3) + ret = sigma_read(result, ARRAY_SIZE(result), devc); + if (ret != ARRAY_SIZE(result)) goto err; - if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) goto err; return SR_OK; + err: sr_err("Configuration failed. Invalid reply received."); return SR_ERR; @@ -381,24 +428,27 @@ err: static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, uint8_t **bb_cmd, gsize *bb_cmd_size) { - size_t i, file_size, bb_size; - char *firmware; - uint8_t *bb_stream, *bbs; + uint8_t *firmware; + size_t file_size; + uint8_t *p; + size_t l; uint32_t imm; - int bit, v; - int ret = SR_OK; + size_t bb_size; + uint8_t *bb_stream, *bbs, byte, mask, v; /* Retrieve the on-disk firmware file content. */ - firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, - name, &file_size, 256 * 1024); + firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name, + &file_size, SIGMA_FIRMWARE_SIZE_LIMIT); if (!firmware) - return SR_ERR; + return SR_ERR_IO; /* Unscramble the file content (XOR with "random" sequence). */ + p = firmware; + l = file_size; imm = 0x3f6df2ab; - for (i = 0; i < file_size; i++) { + while (l--) { imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); - firmware[i] ^= imm & 0xff; + *p++ ^= imm & 0xff; } /* @@ -417,28 +467,32 @@ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, * the bitbang samples, and release the allocated memory. */ bb_size = file_size * 8 * 2; - bb_stream = (uint8_t *)g_try_malloc(bb_size); + bb_stream = g_try_malloc(bb_size); if (!bb_stream) { sr_err("%s: Failed to allocate bitbang stream", __func__); - ret = SR_ERR_MALLOC; - goto exit; + g_free(firmware); + return SR_ERR_MALLOC; } bbs = bb_stream; - for (i = 0; i < file_size; i++) { - for (bit = 7; bit >= 0; bit--) { - v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; - *bbs++ = v | 0x01; + p = firmware; + l = file_size; + while (l--) { + byte = *p++; + mask = 0x80; + while (mask) { + v = (byte & mask) ? BB_PIN_DIN : 0; + mask >>= 1; + *bbs++ = v | BB_PIN_CCLK; *bbs++ = v; } } + g_free(firmware); /* The transformation completed successfully, return the result. */ *bb_cmd = bb_stream; *bb_cmd_size = bb_size; -exit: - g_free(firmware); - return ret; + return SR_OK; } static int upload_firmware(struct sr_context *ctx, @@ -448,39 +502,35 @@ static int upload_firmware(struct sr_context *ctx, unsigned char *buf; unsigned char pins; size_t buf_size; - const char *firmware = sigma_firmware_files[firmware_idx]; - struct ftdi_context *ftdic = &devc->ftdic; + const char *firmware; - /* Make sure it's an ASIX SIGMA. */ - ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, - USB_DESCRIPTION, NULL); - if (ret < 0) { - sr_err("ftdi_usb_open failed: %s", - ftdi_get_error_string(ftdic)); - return 0; + /* Avoid downloading the same firmware multiple times. */ + firmware = firmware_files[firmware_idx]; + if (devc->cur_firmware == firmware_idx) { + sr_info("Not uploading firmware file '%s' again.", firmware); + return SR_OK; } - ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); + /* Set the cable to bitbang mode. */ + ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG); if (ret < 0) { sr_err("ftdi_set_bitmode failed: %s", - ftdi_get_error_string(ftdic)); - return 0; + ftdi_get_error_string(&devc->ftdic)); + return SR_ERR; } - - /* Four times the speed of sigmalogan - Works well. */ - ret = ftdi_set_baudrate(ftdic, 750 * 1000); + ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE); if (ret < 0) { sr_err("ftdi_set_baudrate failed: %s", - ftdi_get_error_string(ftdic)); - return 0; + ftdi_get_error_string(&devc->ftdic)); + return SR_ERR; } - /* Initialize the FPGA for firmware upload. */ + /* Initiate FPGA configuration mode. */ ret = sigma_fpga_init_bitbang(devc); if (ret) return ret; - /* Prepare firmware. */ + /* Prepare wire format of the firmware image. */ ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); if (ret != SR_OK) { sr_err("An error occurred while reading the firmware: %s", @@ -488,22 +538,20 @@ static int upload_firmware(struct sr_context *ctx, return ret; } - /* Upload firmware. */ + /* Write the FPGA netlist to the cable. */ sr_info("Uploading firmware file '%s'.", firmware); sigma_write(buf, buf_size, devc); g_free(buf); - ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); + /* Leave bitbang mode and discard pending input data. */ + ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET); if (ret < 0) { sr_err("ftdi_set_bitmode failed: %s", - ftdi_get_error_string(ftdic)); + ftdi_get_error_string(&devc->ftdic)); return SR_ERR; } - - ftdi_usb_purge_buffers(ftdic); - - /* Discard garbage. */ + ftdi_usb_purge_buffers(&devc->ftdic); while (sigma_read(&pins, 1, devc) == 1) ; @@ -512,24 +560,50 @@ static int upload_firmware(struct sr_context *ctx, if (ret != SR_OK) return ret; + /* Keep track of successful firmware download completion. */ devc->cur_firmware = firmware_idx; - sr_info("Firmware uploaded."); return SR_OK; } +/* + * Sigma doesn't support limiting the number of samples, so we have to + * translate the number and the samplerate to an elapsed time. + * + * In addition we need to ensure that the last data cluster has passed + * the hardware pipeline, and became available to the PC side. With RLE + * compression up to 327ms could pass before another cluster accumulates + * at 200kHz samplerate when input pins don't change. + */ +SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc, + uint64_t limit_samples) +{ + uint64_t limit_msec; + uint64_t worst_cluster_time_ms; + + limit_msec = limit_samples * 1000 / devc->cur_samplerate; + worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate; + /* + * One cluster time is not enough to flush pipeline when sampling + * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix. + */ + return limit_msec + 2 * worst_cluster_time_ms; +} + SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) { struct dev_context *devc; struct drv_context *drvc; size_t i; int ret; + int num_channels; devc = sdi->priv; drvc = sdi->driver->context; ret = SR_OK; + /* Reject rates that are not in the list of supported rates. */ for (i = 0; i < samplerates_count; i++) { if (samplerates[i] == samplerate) break; @@ -537,24 +611,47 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t sampler if (i >= samplerates_count || samplerates[i] == 0) return SR_ERR_SAMPLERATE; + /* + * Depending on the samplerates of 200/100/50- MHz, specific + * firmware is required and higher rates might limit the set + * of available channels. + */ + num_channels = devc->num_channels; if (samplerate <= SR_MHZ(50)) { ret = upload_firmware(drvc->sr_ctx, 0, devc); - devc->num_channels = 16; + num_channels = 16; } else if (samplerate == SR_MHZ(100)) { ret = upload_firmware(drvc->sr_ctx, 1, devc); - devc->num_channels = 8; + num_channels = 8; } else if (samplerate == SR_MHZ(200)) { ret = upload_firmware(drvc->sr_ctx, 2, devc); - devc->num_channels = 4; + num_channels = 4; } + /* + * Derive the sample period from the sample rate as well as the + * number of samples that the device will communicate within + * an "event" (memory organization internal to the device). + */ if (ret == SR_OK) { + devc->num_channels = num_channels; devc->cur_samplerate = samplerate; - devc->period_ps = 1000000000000ULL / samplerate; devc->samples_per_event = 16 / devc->num_channels; devc->state.state = SIGMA_IDLE; } + /* + * Support for "limit_samples" is implemented by stopping + * acquisition after a corresponding period of time. + * Re-calculate that period of time, in case the limit is + * set first and the samplerate gets (re-)configured later. + */ + if (ret == SR_OK && devc->limit_samples) { + uint64_t msecs; + msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples); + devc->limit_msec = msecs; + } + return ret; } @@ -612,16 +709,13 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) if (match->match == SR_TRIGGER_ONE) { devc->trigger.simplevalue |= channelbit; devc->trigger.simplemask |= channelbit; - } - else if (match->match == SR_TRIGGER_ZERO) { + } else if (match->match == SR_TRIGGER_ZERO) { devc->trigger.simplevalue &= ~channelbit; devc->trigger.simplemask |= channelbit; - } - else if (match->match == SR_TRIGGER_FALLING) { + } else if (match->match == SR_TRIGGER_FALLING) { devc->trigger.fallingmask |= channelbit; trigger_set++; - } - else if (match->match == SR_TRIGGER_RISING) { + } else if (match->match == SR_TRIGGER_RISING) { devc->trigger.risingmask |= channelbit; trigger_set++; } @@ -643,7 +737,6 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) return SR_OK; } - /* Software trigger to determine exact trigger position. */ static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, struct sigma_trigger *t) @@ -685,6 +778,101 @@ static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; } +/* + * Return one 16bit data entity of a DRAM cluster at the specified index. + */ +static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx) +{ + uint16_t sample; + + sample = 0; + sample |= cl->samples[idx].sample_lo << 0; + sample |= cl->samples[idx].sample_hi << 8; + sample = (sample >> 8) | (sample << 8); + return sample; +} + +/* + * Deinterlace sample data that was retrieved at 100MHz samplerate. + * One 16bit item contains two samples of 8bits each. The bits of + * multiple samples are interleaved. + */ +static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx) +{ + uint16_t outdata; + + indata >>= idx; + outdata = 0; + outdata |= (indata >> (0 * 2 - 0)) & (1 << 0); + outdata |= (indata >> (1 * 2 - 1)) & (1 << 1); + outdata |= (indata >> (2 * 2 - 2)) & (1 << 2); + outdata |= (indata >> (3 * 2 - 3)) & (1 << 3); + outdata |= (indata >> (4 * 2 - 4)) & (1 << 4); + outdata |= (indata >> (5 * 2 - 5)) & (1 << 5); + outdata |= (indata >> (6 * 2 - 6)) & (1 << 6); + outdata |= (indata >> (7 * 2 - 7)) & (1 << 7); + return outdata; +} + +/* + * Deinterlace sample data that was retrieved at 200MHz samplerate. + * One 16bit item contains four samples of 4bits each. The bits of + * multiple samples are interleaved. + */ +static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx) +{ + uint16_t outdata; + + indata >>= idx; + outdata = 0; + outdata |= (indata >> (0 * 4 - 0)) & (1 << 0); + outdata |= (indata >> (1 * 4 - 1)) & (1 << 1); + outdata |= (indata >> (2 * 4 - 2)) & (1 << 2); + outdata |= (indata >> (3 * 4 - 3)) & (1 << 3); + return outdata; +} + +static void store_sr_sample(uint8_t *samples, int idx, uint16_t data) +{ + samples[2 * idx + 0] = (data >> 0) & 0xff; + samples[2 * idx + 1] = (data >> 8) & 0xff; +} + +/* + * Local wrapper around sr_session_send() calls. Make sure to not send + * more samples to the session's datafeed than what was requested by a + * previously configured (optional) sample count. + */ +static void sigma_session_send(struct sr_dev_inst *sdi, + struct sr_datafeed_packet *packet) +{ + struct dev_context *devc; + struct sr_datafeed_logic *logic; + uint64_t send_now; + + devc = sdi->priv; + if (devc->limit_samples) { + logic = (void *)packet->payload; + send_now = logic->length / logic->unitsize; + if (devc->sent_samples + send_now > devc->limit_samples) { + send_now = devc->limit_samples - devc->sent_samples; + logic->length = send_now * logic->unitsize; + } + if (!send_now) + return; + devc->sent_samples += send_now; + } + + sr_session_send(sdi, packet); +} + +/* + * This size translates to: number of events per row (strictly speaking + * 448, assuming "up to 512" does not harm here) times the sample data's + * unit size (16 bits), times the maximum number of samples per event (4). + */ +#define SAMPLES_BUFFER_SIZE (ROW_LENGTH_U16 * sizeof(uint16_t) * 4) + static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, unsigned int events_in_cluster, unsigned int triggered, @@ -694,13 +882,16 @@ static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, struct sigma_state *ss = &devc->state; struct sr_datafeed_packet packet; struct sr_datafeed_logic logic; - uint16_t tsdiff, ts; - uint8_t samples[2048]; + uint16_t tsdiff, ts, sample, item16; + uint8_t samples[SAMPLES_BUFFER_SIZE]; + uint8_t *send_ptr; + size_t send_count, trig_count; unsigned int i; + int j; ts = sigma_dram_cluster_ts(dram_cluster); tsdiff = ts - ss->lastts; - ss->lastts = ts; + ss->lastts = ts + EVENTS_PER_CLUSTER; packet.type = SR_DF_LOGIC; packet.payload = &logic; @@ -708,42 +899,70 @@ static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, logic.data = samples; /* - * First of all, send Sigrok a copy of the last sample from - * previous cluster as many times as needed to make up for - * the differential characteristics of data we get from the - * Sigma. Sigrok needs one sample of data per period. + * If this cluster is not adjacent to the previously received + * cluster, then send the appropriate number of samples with the + * previous values to the sigrok session. This "decodes RLE". * - * One DRAM cluster contains a timestamp and seven samples, - * the units of timestamp are "devc->period_ps" , the first - * sample in the cluster happens at the time of the timestamp - * and the remaining samples happen at timestamp +1...+6 . + * TODO Improve (mostly: generalize) support for queueing data + * before submission to the session bus. This implementation + * happens to work for "up to 1024 samples" despite the "up to + * 512 entities of 16 bits", due to the "up to 4 sample points + * per event" factor. A better implementation would eliminate + * these magic numbers. */ - for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) { + for (ts = 0; ts < tsdiff; ts++) { i = ts % 1024; - samples[2 * i + 0] = ss->lastsample & 0xff; - samples[2 * i + 1] = ss->lastsample >> 8; + store_sr_sample(samples, i, ss->lastsample); /* * If we have 1024 samples ready or we're at the * end of submitting the padding samples, submit - * the packet to Sigrok. + * the packet to Sigrok. Since constant data is + * sent, duplication of data for rates above 50MHz + * is simple. */ - if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) { + if ((i == 1023) || (ts == tsdiff - 1)) { logic.length = (i + 1) * logic.unitsize; - sr_session_send(sdi, &packet); + for (j = 0; j < devc->samples_per_event; j++) + sigma_session_send(sdi, &packet); } } /* * Parse the samples in current cluster and prepare them - * to be submitted to Sigrok. + * to be submitted to Sigrok. Cope with memory layouts that + * vary with the samplerate. */ + send_ptr = &samples[0]; + send_count = 0; + sample = 0; for (i = 0; i < events_in_cluster; i++) { - samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; - samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; + item16 = sigma_dram_cluster_data(dram_cluster, i); + if (devc->cur_samplerate == SR_MHZ(200)) { + sample = sigma_deinterlace_200mhz_data(item16, 0); + store_sr_sample(samples, send_count++, sample); + sample = sigma_deinterlace_200mhz_data(item16, 1); + store_sr_sample(samples, send_count++, sample); + sample = sigma_deinterlace_200mhz_data(item16, 2); + store_sr_sample(samples, send_count++, sample); + sample = sigma_deinterlace_200mhz_data(item16, 3); + store_sr_sample(samples, send_count++, sample); + } else if (devc->cur_samplerate == SR_MHZ(100)) { + sample = sigma_deinterlace_100mhz_data(item16, 0); + store_sr_sample(samples, send_count++, sample); + sample = sigma_deinterlace_100mhz_data(item16, 1); + store_sr_sample(samples, send_count++, sample); + } else { + sample = item16; + store_sr_sample(samples, send_count++, sample); + } } - /* Send data up to trigger point (if triggered). */ + /* + * If a trigger position applies, then provide the datafeed with + * the first part of data up to that position, then send the + * trigger marker. + */ int trigger_offset = 0; if (triggered) { /* @@ -756,30 +975,31 @@ static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, ss->lastsample, &devc->trigger); if (trigger_offset > 0) { + trig_count = trigger_offset * devc->samples_per_event; packet.type = SR_DF_LOGIC; - logic.length = trigger_offset * logic.unitsize; - sr_session_send(sdi, &packet); - events_in_cluster -= trigger_offset; + logic.length = trig_count * logic.unitsize; + sigma_session_send(sdi, &packet); + send_ptr += trig_count * logic.unitsize; + send_count -= trig_count; } /* Only send trigger if explicitly enabled. */ - if (devc->use_triggers) { - packet.type = SR_DF_TRIGGER; - sr_session_send(sdi, &packet); - } + if (devc->use_triggers) + std_session_send_df_trigger(sdi); } - if (events_in_cluster > 0) { + /* + * Send the data after the trigger, or all of the received data + * if no trigger position applies. + */ + if (send_count) { packet.type = SR_DF_LOGIC; - logic.length = events_in_cluster * logic.unitsize; - logic.data = samples + (trigger_offset * logic.unitsize); - sr_session_send(sdi, &packet); + logic.length = send_count * logic.unitsize; + logic.data = send_ptr; + sigma_session_send(sdi, &packet); } - ss->lastsample = - samples[2 * (events_in_cluster - 1) + 0] | - (samples[2 * (events_in_cluster - 1) + 1] << 8); - + ss->lastsample = sample; } /* @@ -797,15 +1017,21 @@ static int decode_chunk_ts(struct sigma_dram_line *dram_line, struct sr_dev_inst *sdi) { struct sigma_dram_cluster *dram_cluster; - struct dev_context *devc = sdi->priv; - unsigned int clusters_in_line = - (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; + struct dev_context *devc; + unsigned int clusters_in_line; unsigned int events_in_cluster; unsigned int i; - uint32_t trigger_cluster = ~0, triggered = 0; + uint32_t trigger_cluster, triggered; + + devc = sdi->priv; + clusters_in_line = events_in_line; + clusters_in_line += EVENTS_PER_CLUSTER - 1; + clusters_in_line /= EVENTS_PER_CLUSTER; + trigger_cluster = ~0; + triggered = 0; /* Check if trigger is in this chunk. */ - if (trigger_event < (64 * 7)) { + if (trigger_event < EVENTS_PER_ROW) { if (devc->cur_samplerate <= SR_MHZ(50)) { trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, trigger_event); @@ -837,54 +1063,86 @@ static int decode_chunk_ts(struct sigma_dram_line *dram_line, static int download_capture(struct sr_dev_inst *sdi) { - struct dev_context *devc = sdi->priv; const uint32_t chunks_per_read = 32; + + struct dev_context *devc; struct sigma_dram_line *dram_line; int bufsz; uint32_t stoppos, triggerpos; uint8_t modestatus; - uint32_t i; uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; - uint32_t dl_events_in_line = 64 * 7; - uint32_t trg_line = ~0, trg_event = ~0; + uint32_t dl_first_line, dl_line; + uint32_t dl_events_in_line; + uint32_t trg_line, trg_event; - dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); - if (!dram_line) - return FALSE; + devc = sdi->priv; + dl_events_in_line = EVENTS_PER_ROW; sr_info("Downloading sample data."); + devc->state.state = SIGMA_DOWNLOAD; - /* Stop acquisition. */ - sigma_set_register(WRITE_MODE, 0x11, devc); + /* + * Ask the hardware to stop data acquisition. Reception of the + * FORCESTOP request makes the hardware "disable RLE" (store + * clusters to DRAM regardless of whether pin state changes) and + * raise the POSTTRIGGERED flag. + */ + sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc); + do { + if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) { + sr_err("failed while waiting for RMR_POSTTRIGGERED bit"); + return FALSE; + } + } while (!(modestatus & RMR_POSTTRIGGERED)); /* Set SDRAM Read Enable. */ - sigma_set_register(WRITE_MODE, 0x02, devc); + sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc); /* Get the current position. */ sigma_read_pos(&stoppos, &triggerpos, devc); /* Check if trigger has fired. */ - modestatus = sigma_get_register(READ_MODE, devc); - if (modestatus & 0x20) { + if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) { + sr_err("failed to read READ_MODE register"); + return FALSE; + } + trg_line = ~0; + trg_event = ~0; + if (modestatus & RMR_TRIGGERED) { trg_line = triggerpos >> 9; trg_event = triggerpos & 0x1ff; } + devc->sent_samples = 0; + /* - * Determine how many 1024b "DRAM lines" do we need to read from the - * Sigma so we have a complete set of samples. Note that the last - * line can be only partial, containing less than 64 clusters. + * Determine how many "DRAM lines" of 1024 bytes each we need to + * retrieve from the Sigma hardware, so that we have a complete + * set of samples. Note that the last line need not contain 64 + * clusters, it might be partially filled only. + * + * When RMR_ROUND is set, the circular buffer in DRAM has wrapped + * around. Since the status of the very next line is uncertain in + * that case, we skip it and start reading from the next line. */ - dl_lines_total = (stoppos >> 9) + 1; - + dl_first_line = 0; + dl_lines_total = (stoppos >> ROW_SHIFT) + 1; + if (modestatus & RMR_ROUND) { + dl_first_line = dl_lines_total + 1; + dl_lines_total = ROW_COUNT - 2; + } + dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); + if (!dram_line) + return FALSE; dl_lines_done = 0; - while (dl_lines_total > dl_lines_done) { /* We can download only up-to 32 DRAM lines in one go! */ - dl_lines_curr = MIN(chunks_per_read, dl_lines_total); + dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done); - bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, + dl_line = dl_first_line + dl_lines_done; + dl_line %= ROW_COUNT; + bufsz = sigma_read_dram(dl_line, dl_lines_curr, (uint8_t *)dram_line, devc); /* TODO: Check bufsz. For now, just avoid compiler warnings. */ (void)bufsz; @@ -912,45 +1170,38 @@ static int download_capture(struct sr_dev_inst *sdi) dl_lines_done += dl_lines_curr; } + g_free(dram_line); std_session_send_df_end(sdi); - sdi->driver->dev_acquisition_stop(sdi); - - g_free(dram_line); + devc->state.state = SIGMA_IDLE; + sr_dev_acquisition_stop(sdi); return TRUE; } /* - * Handle the Sigma when in CAPTURE mode. This function checks: - * - Sampling time ended - * - DRAM capacity overflow - * This function triggers download of the samples from Sigma - * in case either of the above conditions is true. + * Periodically check the Sigma status when in CAPTURE mode. This routine + * checks whether the configured sample count or sample time have passed, + * and will stop acquisition and download the acquired samples. */ static int sigma_capture_mode(struct sr_dev_inst *sdi) { - struct dev_context *devc = sdi->priv; - + struct dev_context *devc; uint64_t running_msec; - struct timeval tv; + uint64_t current_time; - uint32_t stoppos, triggerpos; + devc = sdi->priv; - /* Check if the selected sampling duration passed. */ - gettimeofday(&tv, 0); - running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + - (tv.tv_usec - devc->start_tv.tv_usec) / 1000; + /* + * Check if the selected sampling duration passed. Sample count + * limits are covered by this enforced timeout as well. + */ + current_time = g_get_monotonic_time(); + running_msec = (current_time - devc->start_time) / 1000; if (running_msec >= devc->limit_msec) return download_capture(sdi); - /* Get the position in DRAM to which the FPGA is writing now. */ - sigma_read_pos(&stoppos, &triggerpos, devc); - /* Test if DRAM is full and if so, download the data. */ - if ((stoppos >> 9) == 32767) - return download_capture(sdi); - return TRUE; } @@ -968,6 +1219,14 @@ SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) if (devc->state.state == SIGMA_IDLE) return TRUE; + /* + * When the application has requested to stop the acquisition, + * then immediately start downloading sample data. Otherwise + * keep checking configured limits which will terminate the + * acquisition and initiate download. + */ + if (devc->state.state == SIGMA_STOPPING) + return download_capture(sdi); if (devc->state.state == SIGMA_CAPTURE) return sigma_capture_mode(sdi);