X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.c;h=e87795e8e6e82ee6067797bd6738b485953c9935;hb=ea57157d0d2e17e418463cf8e4f25453e5b903d7;hp=6dfa7afdd3a53e9bc404afa702f7a5fc048997d8;hpb=0f017b7da90c4379580bf74716dacf0b0f60e292;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c index 6dfa7afd..e87795e8 100644 --- a/src/hardware/asix-sigma/protocol.c +++ b/src/hardware/asix-sigma/protocol.c @@ -382,7 +382,7 @@ static int sigma_read_pos(struct dev_context *devc, } static int sigma_read_dram(struct dev_context *devc, - uint16_t startchunk, size_t numchunks, uint8_t *data) + size_t startchunk, size_t numchunks, uint8_t *data) { uint8_t buf[128], *wrptr, regval; size_t chunk; @@ -432,83 +432,96 @@ static int sigma_read_dram(struct dev_context *devc, SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, struct triggerlut *lut) { - int lut_addr; - uint8_t tmp[2]; + size_t lut_addr; uint16_t bit; - uint8_t buf[6], *wrptr, regval; + uint8_t m3d, m2d, m1d, m0d; + uint8_t buf[6], *wrptr, v8; + uint16_t selreg; int ret; - /* Transpose the table and send to Sigma. */ + /* + * Translate the LUT part of the trigger configuration from the + * application's perspective to the hardware register's bitfield + * layout. Send the LUT to the device. This configures the logic + * which combines pin levels or edges. + */ for (lut_addr = 0; lut_addr < 16; lut_addr++) { - bit = 1 << lut_addr; + bit = BIT(lut_addr); - tmp[0] = tmp[1] = 0; + /* - M4 M3S M3Q */ + m3d = 0; + if (lut->m4 & bit) + m3d |= BIT(2); + if (lut->m3s & bit) + m3d |= BIT(1); + if (lut->m3q & bit) + m3d |= BIT(0); - if (lut->m2d[0] & bit) - tmp[0] |= 0x01; - if (lut->m2d[1] & bit) - tmp[0] |= 0x02; - if (lut->m2d[2] & bit) - tmp[0] |= 0x04; + /* M2D3 M2D2 M2D1 M2D0 */ + m2d = 0; if (lut->m2d[3] & bit) - tmp[0] |= 0x08; + m2d |= BIT(3); + if (lut->m2d[2] & bit) + m2d |= BIT(2); + if (lut->m2d[1] & bit) + m2d |= BIT(1); + if (lut->m2d[0] & bit) + m2d |= BIT(0); - if (lut->m3 & bit) - tmp[0] |= 0x10; - if (lut->m3s & bit) - tmp[0] |= 0x20; - if (lut->m4 & bit) - tmp[0] |= 0x40; + /* M1D3 M1D2 M1D1 M1D0 */ + m1d = 0; + if (lut->m1d[3] & bit) + m1d |= BIT(3); + if (lut->m1d[2] & bit) + m1d |= BIT(2); + if (lut->m1d[1] & bit) + m1d |= BIT(1); + if (lut->m1d[0] & bit) + m1d |= BIT(0); - if (lut->m0d[0] & bit) - tmp[1] |= 0x01; - if (lut->m0d[1] & bit) - tmp[1] |= 0x02; - if (lut->m0d[2] & bit) - tmp[1] |= 0x04; + /* M0D3 M0D2 M0D1 M0D0 */ + m0d = 0; if (lut->m0d[3] & bit) - tmp[1] |= 0x08; - - if (lut->m1d[0] & bit) - tmp[1] |= 0x10; - if (lut->m1d[1] & bit) - tmp[1] |= 0x20; - if (lut->m1d[2] & bit) - tmp[1] |= 0x40; - if (lut->m1d[3] & bit) - tmp[1] |= 0x80; + m0d |= BIT(3); + if (lut->m0d[2] & bit) + m0d |= BIT(2); + if (lut->m0d[1] & bit) + m0d |= BIT(1); + if (lut->m0d[0] & bit) + m0d |= BIT(0); /* - * This logic seems redundant, but separates the value - * determination from the wire format, and is useful - * during future maintenance and research. + * Send 16bits with M3D/M2D and M1D/M0D bit masks to the + * TriggerSelect register, then strobe the LUT write by + * passing A3-A0 to TriggerSelect2. Hold RESET during LUT + * programming. */ wrptr = buf; - write_u8_inc(&wrptr, tmp[0]); - write_u8_inc(&wrptr, tmp[1]); + write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0)); + write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0)); ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); if (ret != SR_OK) return ret; - ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, - TRGSEL2_RESET | TRGSEL2_LUT_WRITE | - (lut_addr & TRGSEL2_LUT_ADDR_MASK)); + v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE | + (lut_addr & TRGSEL2_LUT_ADDR_MASK); + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8); if (ret != SR_OK) return ret; } - /* Send the parameters */ + /* + * Send the parameters. This covers counters and durations. + */ wrptr = buf; - regval = 0; - regval |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT; - regval |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT; - write_u8_inc(&wrptr, regval); - regval = 0; - regval |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT; - regval |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT; - regval |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT; - regval |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT; - write_u8_inc(&wrptr, regval); + selreg = 0; + selreg |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT; + selreg |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT; + selreg |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT; + selreg |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT; + selreg |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT; + selreg |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT; + write_u16be_inc(&wrptr, selreg); write_u16be_inc(&wrptr, lut->params.cmpb); write_u16be_inc(&wrptr, lut->params.cmpa); ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); @@ -540,14 +553,14 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, * mode and sending configuration data. Set D7 and toggle D2, D3, D4 * a few times. */ -#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */ -#define BB_PIN_PROG (1 << 1) /* D1, PROG */ -#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */ -#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */ -#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */ -#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */ -#define BB_PIN_DIN (1 << 6) /* D6, DIN */ -#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */ +#define BB_PIN_CCLK BIT(0) /* D0, CCLK */ +#define BB_PIN_PROG BIT(1) /* D1, PROG */ +#define BB_PIN_D2 BIT(2) /* D2, (part of) SUICIDE */ +#define BB_PIN_D3 BIT(3) /* D3, (part of) SUICIDE */ +#define BB_PIN_D4 BIT(4) /* D4, (part of) SUICIDE (unused?) */ +#define BB_PIN_INIT BIT(5) /* D5, INIT, input pin */ +#define BB_PIN_DIN BIT(6) /* D6, DIN */ +#define BB_PIN_D7 BIT(7) /* D7, (part of) SUICIDE */ #define BB_BITRATE (750 * 1000) #define BB_PINMASK (0xff & ~BB_PIN_INIT) @@ -588,7 +601,8 @@ static int sigma_fpga_init_bitbang_once(struct dev_context *devc) BB_PIN_CCLK, BB_PIN_CCLK, }; - int retries, ret; + size_t retries; + int ret; uint8_t data; /* Section 2. part 1), do the FPGA suicide. */ @@ -733,7 +747,7 @@ static int sigma_fpga_init_la(struct dev_context *devc) * by the caller of this function. */ static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, - uint8_t **bb_cmd, gsize *bb_cmd_size) + uint8_t **bb_cmd, size_t *bb_cmd_size) { uint8_t *firmware; size_t file_size; @@ -919,10 +933,10 @@ SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) uint64_t worst_cluster_time_ms; uint64_t count_msecs, acquire_msecs; - sr_sw_limits_init(&devc->acq_limits); + sr_sw_limits_init(&devc->limit.acquire); /* Get sample count limit, convert to msecs. */ - ret = sr_sw_limits_config_get(&devc->cfg_limits, + ret = sr_sw_limits_config_get(&devc->limit.config, SR_CONF_LIMIT_SAMPLES, &data); if (ret != SR_OK) return ret; @@ -930,10 +944,10 @@ SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) g_variant_unref(data); count_msecs = 0; if (user_count) - count_msecs = 1000 * user_count / devc->samplerate + 1; + count_msecs = 1000 * user_count / devc->clock.samplerate + 1; /* Get time limit, which is in msecs. */ - ret = sr_sw_limits_config_get(&devc->cfg_limits, + ret = sr_sw_limits_config_get(&devc->limit.config, SR_CONF_LIMIT_MSEC, &data); if (ret != SR_OK) return ret; @@ -950,16 +964,16 @@ SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc) return SR_OK; /* Add some slack, and use that timeout for acquisition. */ - worst_cluster_time_ms = 1000 * 65536 / devc->samplerate; + worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate; acquire_msecs += 2 * worst_cluster_time_ms; data = g_variant_new_uint64(acquire_msecs); - ret = sr_sw_limits_config_set(&devc->acq_limits, + ret = sr_sw_limits_config_set(&devc->limit.acquire, SR_CONF_LIMIT_MSEC, data); g_variant_unref(data); if (ret != SR_OK) return ret; - sr_sw_limits_acquisition_start(&devc->acq_limits); + sr_sw_limits_acquisition_start(&devc->limit.acquire); return SR_OK; } @@ -1001,11 +1015,51 @@ SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate) return SR_ERR_ARG; } -SR_PRIV uint64_t sigma_get_samplerate(const struct sr_dev_inst *sdi) +/* Gets called at probe time. Can seed software settings from hardware state. */ +SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi) +{ + struct dev_context *devc; + int ret; + uint8_t regaddr, regval; + + devc = sdi->priv; + if (!devc) + return SR_ERR_ARG; + + /* Seed configuration values from defaults. */ + devc->firmware_idx = SIGMA_FW_NONE; + devc->clock.samplerate = samplerates[0]; + + /* TODO + * Ideally the device driver could retrieve recently stored + * details from hardware registers, thus re-use user specified + * configuration values across sigrok sessions. Which could + * avoid repeated expensive though unnecessary firmware uploads, + * improve performance and usability. Unfortunately it appears + * that the registers range which is documented as available for + * application use keeps providing 0xff data content. At least + * with the netlist version which ships with sigrok. The same + * was observed with unused registers in the first page. + */ + return SR_ERR_NA; + + /* This is for research, currently does not work yet. */ + ret = sigma_check_open(sdi); + regaddr = 16; + regaddr = 14; + ret = sigma_set_register(devc, regaddr, 'F'); + ret = sigma_get_register(devc, regaddr, ®val); + sr_warn("%s() reg[%u] val[%u] rc[%d]", __func__, regaddr, regval, ret); + ret = sigma_check_close(devc); + return ret; +} + +/* Gets called after successful (volatile) hardware configuration. */ +SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi) { - /* TODO Retrieve value from hardware. */ + /* TODO See above, registers seem to not hold written data. */ (void)sdi; - return samplerates[0]; + return SR_ERR_NA; } SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) @@ -1014,13 +1068,13 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) struct drv_context *drvc; uint64_t samplerate; int ret; - int num_channels; + size_t num_channels; devc = sdi->priv; drvc = sdi->driver->context; /* Accept any caller specified rate which the hardware supports. */ - ret = sigma_normalize_samplerate(devc->samplerate, &samplerate); + ret = sigma_normalize_samplerate(devc->clock.samplerate, &samplerate); if (ret != SR_OK) return ret; @@ -1051,6 +1105,14 @@ SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi) devc->samples_per_event = 16 / devc->num_channels; } + /* + * Store the firmware type and most recently configured samplerate + * in hardware, such that subsequent sessions can start from there. + * This is a "best effort" approach. Failure is non-fatal. + */ + if (ret == SR_OK) + (void)sigma_store_hw_config(sdi); + return ret; } @@ -1095,7 +1157,7 @@ static int alloc_submit_buffer(struct sr_dev_inst *sdi) if (!buffer->sample_data) return SR_ERR_MALLOC; buffer->write_pointer = buffer->sample_data; - sr_sw_limits_init(&devc->feed_limits); + sr_sw_limits_init(&devc->limit.submit); buffer->sdi = sdi; memset(&buffer->logic, 0, sizeof(buffer->logic)); @@ -1115,9 +1177,9 @@ static int setup_submit_limit(struct dev_context *devc) GVariant *data; uint64_t total; - limits = &devc->feed_limits; + limits = &devc->limit.submit; - ret = sr_sw_limits_config_get(&devc->cfg_limits, + ret = sr_sw_limits_config_get(&devc->limit.config, SR_CONF_LIMIT_SAMPLES, &data); if (ret != SR_OK) return ret; @@ -1187,7 +1249,7 @@ static int addto_submit_buffer(struct dev_context *devc, int ret; buffer = devc->buffer; - limits = &devc->feed_limits; + limits = &devc->limit.submit; if (sr_sw_limits_check(limits)) count = 0; @@ -1227,14 +1289,21 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) struct sr_trigger_stage *stage; struct sr_trigger_match *match; const GSList *l, *m; - int channelbit, trigger_set; + uint16_t channelbit; + size_t trigger_set; devc = sdi->priv; memset(&devc->trigger, 0, sizeof(devc->trigger)); + devc->use_triggers = FALSE; trigger = sr_session_trigger_get(sdi->session); if (!trigger) return SR_OK; + if (!ASIX_SIGMA_WITH_TRIGGER) { + sr_warn("Trigger support is not implemented. Ignoring the spec."); + return SR_OK; + } + trigger_set = 0; for (l = trigger->stages; l; l = l->next) { stage = l->data; @@ -1243,8 +1312,8 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) /* Ignore disabled channels with a trigger. */ if (!match->channel->enabled) continue; - channelbit = 1 << match->channel->index; - if (devc->samplerate >= SR_MHZ(100)) { + channelbit = BIT(match->channel->index); + if (devc->clock.samplerate >= SR_MHZ(100)) { /* Fast trigger support. */ if (trigger_set) { sr_err("100/200MHz modes limited to single trigger pin."); @@ -1289,6 +1358,9 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) } } + /* Keep track whether triggers are involved during acquisition. */ + devc->use_triggers = TRUE; + return SR_OK; } @@ -1297,7 +1369,7 @@ static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, struct sigma_trigger *t) { const uint8_t *rdptr; - int i; + size_t i; uint16_t sample; rdptr = samples; @@ -1340,7 +1412,9 @@ static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample * See the previous get_trigger_offset() implementation. This * code needs to get re-used here. */ - (void)devc; + if (!devc->use_triggers) + return FALSE; + (void)sample; (void)get_trigger_offset; @@ -1432,7 +1506,8 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, { struct sigma_state *ss; uint16_t tsdiff, ts, sample, item16; - unsigned int i; + size_t count; + size_t evt; if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER) triggered = FALSE; @@ -1451,7 +1526,6 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, ts = sigma_dram_cluster_ts(dram_cluster); tsdiff = ts - ss->lastts; if (tsdiff > 0) { - size_t count; sample = ss->lastsample; count = tsdiff * devc->samples_per_event; (void)check_and_submit_sample(devc, sample, count, FALSE); @@ -1466,9 +1540,9 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, * buffer depth is neither assumed nor required here. */ sample = 0; - for (i = 0; i < events_in_cluster; i++) { - item16 = sigma_dram_cluster_data(dram_cluster, i); - if (devc->samplerate == SR_MHZ(200)) { + for (evt = 0; evt < events_in_cluster; evt++) { + item16 = sigma_dram_cluster_data(dram_cluster, evt); + if (devc->clock.samplerate == SR_MHZ(200)) { sample = sigma_deinterlace_200mhz_data(item16, 0); check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_200mhz_data(item16, 1); @@ -1477,7 +1551,7 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_200mhz_data(item16, 3); check_and_submit_sample(devc, sample, 1, triggered); - } else if (devc->samplerate == SR_MHZ(100)) { + } else if (devc->clock.samplerate == SR_MHZ(100)) { sample = sigma_deinterlace_100mhz_data(item16, 0); check_and_submit_sample(devc, sample, 1, triggered); sample = sigma_deinterlace_100mhz_data(item16, 1); @@ -1504,19 +1578,19 @@ static int decode_chunk_ts(struct dev_context *devc, size_t events_in_line, size_t trigger_event) { struct sigma_dram_cluster *dram_cluster; - unsigned int clusters_in_line; - unsigned int events_in_cluster; - unsigned int i; - uint32_t trigger_cluster; + size_t clusters_in_line; + size_t events_in_cluster; + size_t cluster; + size_t trigger_cluster; clusters_in_line = events_in_line; clusters_in_line += EVENTS_PER_CLUSTER - 1; clusters_in_line /= EVENTS_PER_CLUSTER; - trigger_cluster = ~0; /* Check if trigger is in this chunk. */ + trigger_cluster = ~0UL; if (trigger_event < EVENTS_PER_ROW) { - if (devc->samplerate <= SR_MHZ(50)) { + if (devc->clock.samplerate <= SR_MHZ(50)) { trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, trigger_event); } @@ -1526,11 +1600,11 @@ static int decode_chunk_ts(struct dev_context *devc, } /* For each full DRAM cluster. */ - for (i = 0; i < clusters_in_line; i++) { - dram_cluster = &dram_line->cluster[i]; + for (cluster = 0; cluster < clusters_in_line; cluster++) { + dram_cluster = &dram_line->cluster[cluster]; /* The last cluster might not be full. */ - if ((i == clusters_in_line - 1) && + if ((cluster == clusters_in_line - 1) && (events_in_line % EVENTS_PER_CLUSTER)) { events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; } else { @@ -1538,7 +1612,7 @@ static int decode_chunk_ts(struct dev_context *devc, } sigma_decode_dram_cluster(devc, dram_cluster, - events_in_cluster, i == trigger_cluster); + events_in_cluster, cluster == trigger_cluster); } return SR_OK; @@ -1552,11 +1626,11 @@ static int download_capture(struct sr_dev_inst *sdi) struct sigma_dram_line *dram_line; uint32_t stoppos, triggerpos; uint8_t modestatus; - uint32_t i; - uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; - uint32_t dl_first_line, dl_line; - uint32_t dl_events_in_line, trigger_event; - uint32_t trg_line, trg_event; + size_t line_idx; + size_t dl_lines_total, dl_lines_curr, dl_lines_done; + size_t dl_first_line, dl_line; + size_t dl_events_in_line, trigger_event; + size_t trg_line, trg_event; int ret; devc = sdi->priv; @@ -1593,8 +1667,10 @@ static int download_capture(struct sr_dev_inst *sdi) sr_err("Could not query capture positions/state."); return FALSE; } - trg_line = ~0; - trg_event = ~0; + if (!devc->use_triggers) + triggerpos = ~0; + trg_line = ~0UL; + trg_event = ~0UL; if (modestatus & RMR_TRIGGERED) { trg_line = triggerpos >> ROW_SHIFT; trg_event = triggerpos & ROW_MASK; @@ -1644,18 +1720,18 @@ static int download_capture(struct sr_dev_inst *sdi) devc->state.lastsample = 0; } - for (i = 0; i < dl_lines_curr; i++) { + for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) { /* The last "DRAM line" need not span its full length. */ dl_events_in_line = EVENTS_PER_ROW; - if (dl_lines_done + i == dl_lines_total - 1) + if (dl_lines_done + line_idx == dl_lines_total - 1) dl_events_in_line = stoppos & ROW_MASK; /* Test if the trigger happened on this line. */ - trigger_event = ~0; - if (dl_lines_done + i == trg_line) + trigger_event = ~0UL; + if (dl_lines_done + line_idx == trg_line) trigger_event = trg_event; - decode_chunk_ts(devc, dram_line + i, + decode_chunk_ts(devc, dram_line + line_idx, dl_events_in_line, trigger_event); } @@ -1683,7 +1759,7 @@ static int sigma_capture_mode(struct sr_dev_inst *sdi) struct dev_context *devc; devc = sdi->priv; - if (sr_sw_limits_check(&devc->acq_limits)) + if (sr_sw_limits_check(&devc->limit.acquire)) return download_capture(sdi); return TRUE; @@ -1718,25 +1794,42 @@ SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) } /* Build a LUT entry used by the trigger functions. */ -static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) +static void build_lut_entry(uint16_t *lut_entry, + uint16_t spec_value, uint16_t spec_mask) { - int i, j, k, bit; - - /* For each quad channel. */ - for (i = 0; i < 4; i++) { - entry[i] = 0xffff; - - /* For each bit in LUT. */ - for (j = 0; j < 16; j++) { + size_t quad, bitidx, ch; + uint16_t quadmask, bitmask; + gboolean spec_value_low, bit_idx_low; - /* For each channel in quad. */ - for (k = 0; k < 4; k++) { - bit = 1 << (i * 4 + k); - - /* Set bit in entry */ - if ((mask & bit) && ((!(value & bit)) != - (!(j & (1 << k))))) - entry[i] &= ~(1 << j); + /* + * For each quad-channel-group, for each bit in the LUT (each + * bit pattern of the channel signals, aka LUT address), for + * each channel in the quad, setup the bit in the LUT entry. + * + * Start from all-ones in the LUT (true, always matches), then + * "pessimize the truthness" for specified conditions. + */ + for (quad = 0; quad < 4; quad++) { + lut_entry[quad] = ~0; + for (bitidx = 0; bitidx < 16; bitidx++) { + for (ch = 0; ch < 4; ch++) { + quadmask = BIT(ch); + bitmask = quadmask << (quad * 4); + if (!(spec_mask & bitmask)) + continue; + /* + * This bit is part of the spec. The + * condition which gets checked here + * (got checked in all implementations + * so far) is uncertain. A bit position + * in the current index' number(!) is + * checked? + */ + spec_value_low = !(spec_value & bitmask); + bit_idx_low = !(bitidx & quadmask); + if (spec_value_low == bit_idx_low) + continue; + lut_entry[quad] &= ~BIT(bitidx); } } } @@ -1744,14 +1837,19 @@ static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) /* Add a logical function to LUT mask. */ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, - int index, int neg, uint16_t *mask) + size_t index, gboolean neg, uint16_t *mask) { - int i, j; - int x[2][2], tmp, a, b, aset, bset, rset; + int x[2][2], a, b, aset, bset, rset; + size_t bitidx; - memset(x, 0, sizeof(x)); + /* + * Beware! The x, a, b, aset, bset, rset variables strictly + * require the limited 0..1 range. They are not interpreted + * as logically true, instead bit arith is done on them. + */ - /* Trigger detect condition. */ + /* Construct a pattern which detects the condition. */ + memset(x, 0, sizeof(x)); switch (oper) { case OP_LEVEL: x[0][1] = 1; @@ -1787,8 +1885,11 @@ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, break; } - /* Transpose if neg is set. */ + /* Transpose the pattern if the condition is negated. */ if (neg) { + size_t i, j; + int tmp; + for (i = 0; i < 2; i++) { for (j = 0; j < 2; j++) { tmp = x[i][j]; @@ -1798,29 +1899,30 @@ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, } } - /* Update mask with function. */ - for (i = 0; i < 16; i++) { - a = (i >> (2 * index + 0)) & 1; - b = (i >> (2 * index + 1)) & 1; + /* Update the LUT mask with the function's condition. */ + for (bitidx = 0; bitidx < 16; bitidx++) { + a = (bitidx & BIT(2 * index + 0)) ? 1 : 0; + b = (bitidx & BIT(2 * index + 1)) ? 1 : 0; - aset = (*mask >> i) & 1; + aset = (*mask & BIT(bitidx)) ? 1 : 0; bset = x[b][a]; - rset = 0; if (func == FUNC_AND || func == FUNC_NAND) rset = aset & bset; else if (func == FUNC_OR || func == FUNC_NOR) rset = aset | bset; else if (func == FUNC_XOR || func == FUNC_NXOR) rset = aset ^ bset; + else + rset = 0; if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) - rset = !rset; - - *mask &= ~(1 << i); + rset = 1 - rset; if (rset) - *mask |= 1 << i; + *mask |= BIT(bitidx); + else + *mask &= ~BIT(bitidx); } } @@ -1832,47 +1934,59 @@ static void add_trigger_function(enum triggerop oper, enum triggerfunc func, SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, struct triggerlut *lut) { - int i, j; uint16_t masks[2]; + size_t bitidx, condidx; + uint16_t value, mask; + /* Setup something that "won't match" in the absence of a spec. */ memset(lut, 0, sizeof(*lut)); - memset(&masks, 0, sizeof(masks)); + if (!devc->use_triggers) + return SR_OK; - /* Constant for simple triggers. */ + /* Start assuming simple triggers. Edges are handled below. */ lut->m4 = 0xa000; + lut->m3q = 0xffff; - /* Value/mask trigger support. */ - build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, - lut->m2d); + /* Process value/mask triggers. */ + value = devc->trigger.simplevalue; + mask = devc->trigger.simplemask; + build_lut_entry(lut->m2d, value, mask); - /* Rise/fall trigger support. */ - for (i = 0, j = 0; i < 16; i++) { - if (devc->trigger.risingmask & (1 << i) || - devc->trigger.fallingmask & (1 << i)) - masks[j++] = 1 << i; + /* Scan for and process rise/fall triggers. */ + memset(&masks, 0, sizeof(masks)); + condidx = 0; + for (bitidx = 0; bitidx < 16; bitidx++) { + mask = BIT(bitidx); + value = devc->trigger.risingmask | devc->trigger.fallingmask; + if (!(value & mask)) + continue; + if (condidx == 0) + build_lut_entry(lut->m0d, mask, mask); + if (condidx == 1) + build_lut_entry(lut->m1d, mask, mask); + masks[condidx++] = mask; + if (condidx == ARRAY_SIZE(masks)) + break; } - build_lut_entry(masks[0], masks[0], lut->m0d); - build_lut_entry(masks[1], masks[1], lut->m1d); - - /* Add glue logic */ + /* Add glue logic for rise/fall triggers. */ if (masks[0] || masks[1]) { - /* Transition trigger. */ + lut->m3q = 0; if (masks[0] & devc->trigger.risingmask) - add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); + add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3q); if (masks[0] & devc->trigger.fallingmask) - add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); + add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3q); if (masks[1] & devc->trigger.risingmask) - add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); + add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3q); if (masks[1] & devc->trigger.fallingmask) - add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); - } else { - /* Only value/mask trigger. */ - lut->m3 = 0xffff; + add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3q); } /* Triggertype: event. */ - lut->params.selres = 3; + lut->params.selres = TRGSEL_SELCODE_NEVER; + lut->params.selinc = TRGSEL_SELCODE_LEVEL; + lut->params.sela = 0; /* Counter >= CMPA && LEVEL */ + lut->params.cmpa = 0; /* Count 0 -> 1 already triggers. */ return SR_OK; }