X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fprotocol.c;h=2c00d74dd266612e0d4fcf882f7efc4c81af8164;hb=8a72362505408849fb0d04d7df22a3c54a1aee73;hp=edddb293b515b552ea60f7e6a74c4fd04a77c09c;hpb=ee5cef710315611b9e48b901c70311f23c99ef95;p=libsigrok.git diff --git a/src/hardware/asix-sigma/protocol.c b/src/hardware/asix-sigma/protocol.c index edddb293..2c00d74d 100644 --- a/src/hardware/asix-sigma/protocol.c +++ b/src/hardware/asix-sigma/protocol.c @@ -435,8 +435,9 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, size_t lut_addr; uint16_t bit; uint8_t m3d, m2d, m1d, m0d; - uint8_t buf[6], *wrptr, v8; - uint16_t selreg; + uint8_t buf[6], *wrptr; + uint8_t trgsel2; + uint16_t lutreg, selreg; int ret; /* @@ -497,15 +498,19 @@ SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, * programming. */ wrptr = buf; - write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0)); - write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0)); + lutreg = 0; + lutreg <<= 4; lutreg |= m3d; + lutreg <<= 4; lutreg |= m2d; + lutreg <<= 4; lutreg |= m1d; + lutreg <<= 4; lutreg |= m0d; + write_u16be_inc(&wrptr, lutreg); ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf); if (ret != SR_OK) return ret; - v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE | + trgsel2 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE | (lut_addr & TRGSEL2_LUT_ADDR_MASK); - ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8); + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trgsel2); if (ret != SR_OK) return ret; } @@ -1250,7 +1255,7 @@ static int addto_submit_buffer(struct dev_context *devc, buffer = devc->buffer; limits = &devc->limit.submit; - if (sr_sw_limits_check(limits)) + if (!devc->use_triggers && sr_sw_limits_check(limits)) count = 0; /* @@ -1267,18 +1272,169 @@ static int addto_submit_buffer(struct dev_context *devc, return ret; } sr_sw_limits_update_samples_read(limits, 1); - if (sr_sw_limits_check(limits)) + if (!devc->use_triggers && sr_sw_limits_check(limits)) break; } return SR_OK; } -static int alloc_sample_buffer(struct dev_context *devc) +static void sigma_location_break_down(struct sigma_location *loc) { + + loc->line = loc->raw / ROW_LENGTH_U16; + loc->line += ROW_COUNT; + loc->line %= ROW_COUNT; + loc->cluster = loc->raw % ROW_LENGTH_U16; + loc->event = loc->cluster % EVENTS_PER_CLUSTER; + loc->cluster = loc->cluster / EVENTS_PER_CLUSTER; +} + +static gboolean sigma_location_is_eq(struct sigma_location *loc1, + struct sigma_location *loc2, gboolean with_event) +{ + + if (!loc1 || !loc2) + return FALSE; + + if (loc1->line != loc2->line) + return FALSE; + if (loc1->cluster != loc2->cluster) + return FALSE; + + if (with_event && loc1->event != loc2->event) + return FALSE; + + return TRUE; +} + +/* Decrement the broken-down location fields (leave 'raw' as is). */ +static void sigma_location_decrement(struct sigma_location *loc, + gboolean with_event) +{ + + if (!loc) + return; + + if (with_event) { + if (loc->event--) + return; + loc->event = EVENTS_PER_CLUSTER - 1; + } + + if (loc->cluster--) + return; + loc->cluster = CLUSTERS_PER_ROW - 1; + + if (loc->line--) + return; + loc->line = ROW_COUNT - 1; +} + +static void sigma_location_increment(struct sigma_location *loc) +{ + + if (!loc) + return; + + if (++loc->event < EVENTS_PER_CLUSTER) + return; + loc->event = 0; + if (++loc->cluster < CLUSTERS_PER_ROW) + return; + loc->cluster = 0; + if (++loc->line < ROW_COUNT) + return; + loc->line = 0; +} + +/* + * Determine the position where to open the period of trigger match + * checks. Setup an "impossible" location when triggers are not used. + * Start from the hardware provided 'trig' position otherwise, and + * go back a few clusters, but don't go before the 'start' position. + */ +static void rewind_trig_arm_pos(struct dev_context *devc, size_t count) +{ + struct sigma_sample_interp *interp; + + if (!devc) + return; + interp = &devc->interp; + + if (!devc->use_triggers) { + interp->trig_arm.raw = ~0; + sigma_location_break_down(&interp->trig_arm); + return; + } + + interp->trig_arm = interp->trig; + while (count--) { + if (sigma_location_is_eq(&interp->trig_arm, &interp->start, TRUE)) + break; + sigma_location_decrement(&interp->trig_arm, TRUE); + } +} + +static int alloc_sample_buffer(struct dev_context *devc, + size_t stop_pos, size_t trig_pos, uint8_t mode) +{ + struct sigma_sample_interp *interp; + gboolean wrapped; size_t alloc_size; - devc->interp.fetch.lines_per_read = 32; + interp = &devc->interp; + + /* + * Either fetch sample memory from absolute start of DRAM to the + * current write position. Or from after the current write position + * to before the current write position, if the write pointer has + * wrapped around at the upper DRAM boundary. Assume that the line + * which most recently got written to is of unknown state, ignore + * its content in the "wrapped" case. + */ + wrapped = mode & RMR_ROUND; + interp->start.raw = 0; + interp->stop.raw = stop_pos; + if (wrapped) { + interp->start.raw = stop_pos; + interp->start.raw >>= ROW_SHIFT; + interp->start.raw++; + interp->start.raw <<= ROW_SHIFT; + interp->stop.raw = stop_pos; + interp->stop.raw >>= ROW_SHIFT; + interp->stop.raw--; + interp->stop.raw <<= ROW_SHIFT; + } + interp->trig.raw = trig_pos; + interp->iter.raw = 0; + + /* Break down raw values to line, cluster, event fields. */ + sigma_location_break_down(&interp->start); + sigma_location_break_down(&interp->stop); + sigma_location_break_down(&interp->trig); + sigma_location_break_down(&interp->iter); + + /* + * The hardware provided trigger location "is late" because of + * latency in hardware pipelines. It points to after the trigger + * condition match. Arrange for a software check of sample data + * matches starting just a little before the hardware provided + * location. The "4 clusters" distance is an arbitrary choice. + */ + rewind_trig_arm_pos(devc, 4 * EVENTS_PER_CLUSTER); + memset(&interp->trig_chk, 0, sizeof(interp->trig_chk)); + + /* Determine which DRAM lines to fetch from the device. */ + memset(&interp->fetch, 0, sizeof(interp->fetch)); + interp->fetch.lines_total = interp->stop.line + 1; + interp->fetch.lines_total -= interp->start.line; + interp->fetch.lines_total += ROW_COUNT; + interp->fetch.lines_total %= ROW_COUNT; + interp->fetch.lines_done = 0; + + /* Arrange for chunked download, N lines per USB request. */ + interp->fetch.lines_per_read = 32; alloc_size = sizeof(devc->interp.fetch.rcvd_lines[0]); alloc_size *= devc->interp.fetch.lines_per_read; devc->interp.fetch.rcvd_lines = g_try_malloc0(alloc_size); @@ -1288,6 +1444,52 @@ static int alloc_sample_buffer(struct dev_context *devc) return SR_OK; } +static uint16_t sigma_deinterlace_data_4x4(uint16_t indata, int idx); +static uint16_t sigma_deinterlace_data_2x8(uint16_t indata, int idx); + +static int fetch_sample_buffer(struct dev_context *devc) +{ + struct sigma_sample_interp *interp; + size_t count; + int ret; + const uint8_t *rdptr; + uint16_t ts, data; + + interp = &devc->interp; + + /* First invocation? Seed the iteration position. */ + if (!interp->fetch.lines_done) { + interp->iter = interp->start; + } + + /* Get another set of DRAM lines in one read call. */ + count = interp->fetch.lines_total - interp->fetch.lines_done; + if (count > interp->fetch.lines_per_read) + count = interp->fetch.lines_per_read; + ret = sigma_read_dram(devc, interp->iter.line, count, + (uint8_t *)interp->fetch.rcvd_lines); + if (ret != SR_OK) + return ret; + interp->fetch.lines_rcvd = count; + interp->fetch.curr_line = &interp->fetch.rcvd_lines[0]; + + /* First invocation? Get initial timestamp and sample data. */ + if (!interp->fetch.lines_done) { + rdptr = (void *)interp->fetch.curr_line; + ts = read_u16le_inc(&rdptr); + data = read_u16le_inc(&rdptr); + if (interp->samples_per_event == 4) { + data = sigma_deinterlace_data_4x4(data, 0); + } else if (interp->samples_per_event == 2) { + data = sigma_deinterlace_data_2x8(data, 0); + } + interp->last.ts = ts; + interp->last.sample = data; + } + + return SR_OK; +} + static void free_sample_buffer(struct dev_context *devc) { g_free(devc->interp.fetch.rcvd_lines); @@ -1384,77 +1586,70 @@ SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) return SR_OK; } -/* Software trigger to determine exact trigger position. */ -static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, - struct sigma_trigger *t) +static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample) { - const uint8_t *rdptr; - size_t i; - uint16_t sample; - - rdptr = samples; - sample = 0; - for (i = 0; i < 8; i++) { - if (i > 0) - last_sample = sample; - sample = read_u16le_inc(&rdptr); - - /* Simple triggers. */ - if ((sample & t->simplemask) != t->simplevalue) - continue; - - /* Rising edge. */ - if (((last_sample & t->risingmask) != 0) || - ((sample & t->risingmask) != t->risingmask)) - continue; - - /* Falling edge. */ - if ((last_sample & t->fallingmask) != t->fallingmask || - (sample & t->fallingmask) != 0) - continue; + struct sigma_sample_interp *interp; + uint16_t last_sample; + struct sigma_trigger *t; + gboolean simple_match, rising_match, falling_match; + gboolean matched; - break; - } + /* + * This logic is about improving the precision of the hardware + * provided trigger match position. Software checks are only + * required for a short range of samples, and only when a user + * specified trigger condition was involved during acquisition. + */ + if (!devc) + return FALSE; + if (!devc->use_triggers) + return FALSE; + interp = &devc->interp; + if (!interp->trig_chk.armed) + return FALSE; - /* If we did not match, return original trigger pos. */ - return i & 0x7; + /* + * Check if the current sample and its most recent transition + * match the initially provided trigger condition. The data + * must not fail either of the individual checks. Unused + * trigger features remain neutral in the summary expression. + */ + last_sample = interp->last.sample; + t = &devc->trigger; + simple_match = (sample & t->simplemask) == t->simplevalue; + rising_match = ((last_sample & t->risingmask) == 0) && + ((sample & t->risingmask) == t->risingmask); + falling_match = ((last_sample & t->fallingmask) == t->fallingmask) && + ((sample & t->fallingmask) == 0); + matched = simple_match && rising_match && falling_match; + + return matched; } -static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample) +static int send_trigger_marker(struct dev_context *devc) { - /* TODO - * Check whether the combination of this very sample and the - * previous state match the configured trigger condition. This - * improves the resolution of the trigger marker's position. - * The hardware provided position is coarse, and may point to - * a position before the actual match. - * - * See the previous get_trigger_offset() implementation. This - * code needs to get re-used here. - */ - if (!devc->use_triggers) - return FALSE; + int ret; - (void)sample; - (void)get_trigger_offset; + ret = flush_submit_buffer(devc); + if (ret != SR_OK) + return ret; + ret = std_session_send_df_trigger(devc->buffer->sdi); + if (ret != SR_OK) + return ret; - return FALSE; + return SR_OK; } static int check_and_submit_sample(struct dev_context *devc, - uint16_t sample, size_t count, gboolean check_trigger) + uint16_t sample, size_t count) { gboolean triggered; int ret; - triggered = check_trigger && sample_matches_trigger(devc, sample); + triggered = sample_matches_trigger(devc, sample); if (triggered) { - ret = flush_submit_buffer(devc); - if (ret != SR_OK) - return ret; - ret = std_session_send_df_trigger(devc->buffer->sdi); - if (ret != SR_OK) - return ret; + send_trigger_marker(devc); + devc->interp.trig_chk.matched = TRUE; } ret = addto_submit_buffer(devc, sample, count); @@ -1464,6 +1659,46 @@ static int check_and_submit_sample(struct dev_context *devc, return SR_OK; } +static void sigma_location_check(struct dev_context *devc) +{ + struct sigma_sample_interp *interp; + + if (!devc) + return; + interp = &devc->interp; + + /* + * Manage the period of trigger match checks in software. + * Start supervision somewhere before the hardware provided + * location. Stop supervision after an arbitrary amount of + * event slots, or when a match was found. + */ + if (interp->trig_chk.armed) { + interp->trig_chk.evt_remain--; + if (!interp->trig_chk.evt_remain || interp->trig_chk.matched) + interp->trig_chk.armed = FALSE; + } + if (!interp->trig_chk.armed && !interp->trig_chk.matched) { + if (sigma_location_is_eq(&interp->iter, &interp->trig_arm, TRUE)) { + interp->trig_chk.armed = TRUE; + interp->trig_chk.matched = FALSE; + interp->trig_chk.evt_remain = 8 * EVENTS_PER_CLUSTER; + } + } + + /* + * Force a trigger marker when the software check found no match + * yet while the hardware provided position was reached. This + * very probably is a user initiated button press. + */ + if (interp->trig_chk.armed) { + if (sigma_location_is_eq(&interp->iter, &interp->trig, TRUE)) { + (void)send_trigger_marker(devc); + interp->trig_chk.matched = TRUE; + } + } +} + /* * Return the timestamp of "DRAM cluster". */ @@ -1546,7 +1781,7 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, if (tsdiff > 0) { sample = devc->interp.last.sample; count = tsdiff * devc->interp.samples_per_event; - (void)check_and_submit_sample(devc, sample, count, FALSE); + (void)check_and_submit_sample(devc, sample, count); } devc->interp.last.ts = ts + EVENTS_PER_CLUSTER; @@ -1562,24 +1797,32 @@ static void sigma_decode_dram_cluster(struct dev_context *devc, item16 = sigma_dram_cluster_data(dram_cluster, evt); if (devc->interp.samples_per_event == 4) { sample = sigma_deinterlace_data_4x4(item16, 0); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; sample = sigma_deinterlace_data_4x4(item16, 1); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; sample = sigma_deinterlace_data_4x4(item16, 2); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; sample = sigma_deinterlace_data_4x4(item16, 3); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; } else if (devc->interp.samples_per_event == 2) { sample = sigma_deinterlace_data_2x8(item16, 0); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; sample = sigma_deinterlace_data_2x8(item16, 1); - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; } else { sample = item16; - check_and_submit_sample(devc, sample, 1, triggered); + check_and_submit_sample(devc, sample, 1); + devc->interp.last.sample = sample; } + sigma_location_increment(&devc->interp.iter); + sigma_location_check(devc); } - devc->interp.last.sample = sample; } /* @@ -1606,7 +1849,7 @@ static int decode_chunk_ts(struct dev_context *devc, clusters_in_line /= EVENTS_PER_CLUSTER; /* Check if trigger is in this chunk. */ - trigger_cluster = ~0UL; + trigger_cluster = ~UINT64_C(0); if (trigger_event < EVENTS_PER_ROW) { if (devc->clock.samplerate <= SR_MHZ(50)) { trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, @@ -1642,11 +1885,6 @@ static int download_capture(struct sr_dev_inst *sdi) struct sigma_sample_interp *interp; uint32_t stoppos, triggerpos; uint8_t modestatus; - size_t line_idx; - size_t dl_lines_total, dl_lines_curr, dl_lines_done; - size_t dl_first_line, dl_line; - size_t dl_events_in_line, trigger_event; - size_t trg_line, trg_event; int ret; devc = sdi->priv; @@ -1660,6 +1898,9 @@ static int download_capture(struct sr_dev_inst *sdi) * FORCESTOP request makes the hardware "disable RLE" (store * clusters to DRAM regardless of whether pin state changes) and * raise the POSTTRIGGERED flag. + * + * Then switch the hardware from DRAM write (data acquisition) + * to DRAM read (sample memory download). */ modestatus = WMR_FORCESTOP | WMR_SDRAMWRITEEN; ret = sigma_set_register(devc, WRITE_MODE, modestatus); @@ -1672,13 +1913,15 @@ static int download_capture(struct sr_dev_inst *sdi) return FALSE; } } while (!(modestatus & RMR_POSTTRIGGERED)); - - /* Set SDRAM Read Enable. */ ret = sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN); if (ret != SR_OK) return ret; - /* Get the current position. Check if trigger has fired. */ + /* + * Get the current positions (acquisition write pointer, and + * trigger match location). With disabled triggers, use a value + * for the location that will never match during interpretation. + */ ret = sigma_read_pos(devc, &stoppos, &triggerpos, &modestatus); if (ret != SR_OK) { sr_err("Could not query capture positions/state."); @@ -1686,77 +1929,46 @@ static int download_capture(struct sr_dev_inst *sdi) } if (!devc->use_triggers) triggerpos = ~0; - trg_line = ~0UL; - trg_event = ~0UL; - if (modestatus & RMR_TRIGGERED) { - trg_line = triggerpos >> ROW_SHIFT; - trg_event = triggerpos & ROW_MASK; - } + if (!(modestatus & RMR_TRIGGERED)) + triggerpos = ~0; /* - * Determine how many "DRAM lines" of 1024 bytes each we need to - * retrieve from the Sigma hardware, so that we have a complete - * set of samples. Note that the last line need not contain 64 - * clusters, it might be partially filled only. - * - * When RMR_ROUND is set, the circular buffer in DRAM has wrapped - * around. Since the status of the very next line is uncertain in - * that case, we skip it and start reading from the next line. + * Determine which area of the sample memory to retrieve, + * allocate a receive buffer, and setup counters/pointers. */ - dl_first_line = 0; - dl_lines_total = (stoppos >> ROW_SHIFT) + 1; - if (modestatus & RMR_ROUND) { - dl_first_line = dl_lines_total + 1; - dl_lines_total = ROW_COUNT - 2; - } - ret = alloc_sample_buffer(devc); + ret = alloc_sample_buffer(devc, stoppos, triggerpos, modestatus); if (ret != SR_OK) return FALSE; + ret = alloc_submit_buffer(sdi); if (ret != SR_OK) return FALSE; ret = setup_submit_limit(devc); if (ret != SR_OK) return FALSE; - dl_lines_done = 0; - while (dl_lines_total > dl_lines_done) { - - /* Get another set of DRAM lines in one read. */ - dl_lines_curr = dl_lines_total - dl_lines_done; - if (dl_lines_curr > interp->fetch.lines_per_read) - dl_lines_curr = interp->fetch.lines_per_read; - dl_line = dl_first_line + dl_lines_done; - dl_line %= ROW_COUNT; - ret = sigma_read_dram(devc, dl_line, dl_lines_curr, - (uint8_t *)interp->fetch.rcvd_lines); + while (interp->fetch.lines_done < interp->fetch.lines_total) { + size_t dl_events_in_line, trigger_event; + + /* Read another chunk of sample memory (several lines). */ + ret = fetch_sample_buffer(devc); if (ret != SR_OK) return FALSE; - interp->fetch.curr_line = &interp->fetch.rcvd_lines[0]; - /* Seed initial timestamp from the first DRAM line. */ - if (dl_lines_done == 0) { - interp->last.ts = - sigma_dram_cluster_ts(&interp->fetch.curr_line->cluster[0]); - interp->last.sample = 0; - } - - for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) { - /* The last "DRAM line" need not span its full length. */ + /* Process lines of sample data. Last line may be short. */ + while (interp->fetch.lines_rcvd--) { dl_events_in_line = EVENTS_PER_ROW; - if (dl_lines_done + line_idx == dl_lines_total - 1) - dl_events_in_line = stoppos & ROW_MASK; - - /* Test if the trigger happened on this line. */ - trigger_event = ~0UL; - if (dl_lines_done + line_idx == trg_line) - trigger_event = trg_event; - + if (interp->iter.line == interp->stop.line) { + dl_events_in_line = interp->stop.raw & ROW_MASK; + } + trigger_event = ~UINT64_C(0); + if (interp->iter.line == interp->trig.line) { + trigger_event = interp->trig.raw & ROW_MASK; + } decode_chunk_ts(devc, interp->fetch.curr_line, dl_events_in_line, trigger_event); interp->fetch.curr_line++; + interp->fetch.lines_done++; } - - dl_lines_done += dl_lines_curr; } flush_submit_buffer(devc); free_submit_buffer(devc);