X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=src%2Fhardware%2Fasix-sigma%2Fapi.c;h=04bc74887de3604b51bec147ba9b1ed5abdcddd8;hb=88a5f9eabe72113d70c29d45dc12eabc0add9c49;hp=5fbd51759f48f32599b587480b109cf134a2b93b;hpb=9b4d261fabf7f9fd70ccd7514ecdadb8e87a7490;p=libsigrok.git diff --git a/src/hardware/asix-sigma/api.c b/src/hardware/asix-sigma/api.c index 5fbd5175..04bc7488 100644 --- a/src/hardware/asix-sigma/api.c +++ b/src/hardware/asix-sigma/api.c @@ -4,6 +4,7 @@ * Copyright (C) 2010-2012 Håvard Espeland , * Copyright (C) 2010 Martin Stensgård * Copyright (C) 2010 Carl Henrik Lunde + * Copyright (C) 2020 Gerhard Sittig * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -405,9 +406,8 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) uint8_t triggerselect; struct triggerinout triggerinout_conf; struct triggerlut lut; - uint8_t regval; - uint8_t clock_bytes[sizeof(clockselect)]; - size_t clock_idx; + uint8_t regval, trgconf_bytes[2], clock_bytes[4], *wrptr; + size_t count; devc = sdi->priv; @@ -427,18 +427,23 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) if (ret != SR_OK) return ret; - if (sigma_convert_trigger(sdi) != SR_OK) { - sr_err("Failed to configure triggers."); - return SR_ERR; + ret = sigma_convert_trigger(sdi); + if (ret != SR_OK) { + sr_err("Could not configure triggers."); + return ret; } /* Enter trigger programming mode. */ - sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x20); + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x20); + if (ret != SR_OK) + return ret; triggerselect = 0; if (devc->samplerate >= SR_MHZ(100)) { /* 100 and 200 MHz mode. */ - sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81); + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81); + if (ret != SR_OK) + return ret; /* Find which pin to trigger on from mask. */ for (triggerpin = 0; triggerpin < 8; triggerpin++) { @@ -449,7 +454,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) } /* Set trigger pin and light LED on trigger. */ - triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); + triggerselect = TRGSEL2_LEDSEL1 | (triggerpin & 0x7); /* Default rising edge. */ if (devc->trigger.fallingmask) @@ -457,34 +462,60 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) } else if (devc->samplerate <= SR_MHZ(50)) { /* All other modes. */ - sigma_build_basic_trigger(devc, &lut); + ret = sigma_build_basic_trigger(devc, &lut); + if (ret != SR_OK) + return ret; - sigma_write_trigger_lut(devc, &lut); + ret = sigma_write_trigger_lut(devc, &lut); + if (ret != SR_OK) + return ret; - triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); + triggerselect = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0; } /* Setup trigger in and out pins to default values. */ - memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); + memset(&triggerinout_conf, 0, sizeof(triggerinout_conf)); triggerinout_conf.trgout_bytrigger = 1; triggerinout_conf.trgout_enable = 1; + /* TODO + * Verify the correctness of this implementation. The previous + * version used to assign to a C language struct with bit fields + * which is highly non-portable and hard to guess the resulting + * raw memory layout or wire transfer content. The C struct's + * field names did not match the vendor documentation's names. + * Which means that I could not verify "on paper" either. Let's + * re-visit this code later during research for trigger support. + */ + wrptr = trgconf_bytes; + regval = 0; + if (triggerinout_conf.trgout_bytrigger) + regval |= TRGOPT_TRGOOUTEN; + write_u8_inc(&wrptr, regval); + regval &= ~TRGOPT_CLEAR_MASK; + if (triggerinout_conf.trgout_enable) + regval |= TRGOPT_TRGOEN; + write_u8_inc(&wrptr, regval); + count = wrptr - trgconf_bytes; + ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION, + trgconf_bytes, count); + if (ret != SR_OK) + return ret; - sigma_write_register(devc, WRITE_TRIGGER_OPTION, - (uint8_t *)&triggerinout_conf, sizeof(struct triggerinout)); - - /* Go back to normal mode. */ - sigma_set_register(devc, WRITE_TRIGGER_SELECT2, triggerselect); + /* Leave trigger programming mode. */ + ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, triggerselect); + if (ret != SR_OK) + return ret; /* Set clock select register. */ clockselect.async = 0; - clockselect.fraction = 1 - 1; /* Divider 1. */ + clockselect.fraction = 1; /* Divider 1. */ clockselect.disabled_channels = 0x0000; /* All channels enabled. */ if (devc->samplerate == SR_MHZ(200)) { /* Enable 4 channels. */ - clockselect.disabled_channels = 0xf0ff; + clockselect.disabled_channels = 0xfff0; } else if (devc->samplerate == SR_MHZ(100)) { /* Enable 8 channels. */ - clockselect.disabled_channels = 0x00ff; + clockselect.disabled_channels = 0xff00; } else { /* * 50 MHz mode, or fraction thereof. The 50MHz reference @@ -493,31 +524,41 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) * (The driver lists a discrete set of sample rates, but * all of them fit the above description.) */ - clockselect.fraction = SR_MHZ(50) / devc->samplerate - 1; + clockselect.fraction = SR_MHZ(50) / devc->samplerate; } - clock_idx = 0; - clock_bytes[clock_idx++] = clockselect.async; - clock_bytes[clock_idx++] = clockselect.fraction; - clock_bytes[clock_idx++] = clockselect.disabled_channels & 0xff; - clock_bytes[clock_idx++] = clockselect.disabled_channels >> 8; - sigma_write_register(devc, WRITE_CLOCK_SELECT, clock_bytes, clock_idx); + wrptr = clock_bytes; + write_u8_inc(&wrptr, clockselect.async); + write_u8_inc(&wrptr, clockselect.fraction - 1); + write_u16be_inc(&wrptr, clockselect.disabled_channels); + count = wrptr - clock_bytes; + ret = sigma_write_register(devc, WRITE_CLOCK_SELECT, clock_bytes, count); + if (ret != SR_OK) + return ret; /* Setup maximum post trigger time. */ - sigma_set_register(devc, WRITE_POST_TRIGGER, + ret = sigma_set_register(devc, WRITE_POST_TRIGGER, (devc->capture_ratio * 255) / 100); + if (ret != SR_OK) + return ret; /* Start acqusition. */ regval = WMR_TRGRES | WMR_SDRAMWRITEEN; #if ASIX_SIGMA_WITH_TRIGGER regval |= WMR_TRGEN; #endif - sigma_set_register(devc, WRITE_MODE, regval); + ret = sigma_set_register(devc, WRITE_MODE, regval); + if (ret != SR_OK) + return ret; - std_session_send_df_header(sdi); + ret = std_session_send_df_header(sdi); + if (ret != SR_OK) + return ret; /* Add capture source. */ - sr_session_source_add(sdi->session, -1, 0, 10, + ret = sr_session_source_add(sdi->session, -1, 0, 10, sigma_receive_data, (void *)sdi); + if (ret != SR_OK) + return ret; devc->state.state = SIGMA_CAPTURE; @@ -541,7 +582,7 @@ static int dev_acquisition_stop(struct sr_dev_inst *sdi) devc->state.state = SIGMA_STOPPING; } else { devc->state.state = SIGMA_IDLE; - sr_session_source_remove(sdi->session, -1); + (void)sr_session_source_remove(sdi->session, -1); } return SR_OK;