X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=onewire%2Fsockit_owm%2FREADME;h=c84e36411d7ec9f731be58eaaff8b4457bf51be4;hb=347cebaaa4b7b397729378388e723b3b8229c6ca;hp=e894f084138aaaa445349db43a8aad0369c6c707;hpb=b636dd75fcc09b8e996a83210262d49a0a9e3cb1;p=sigrok-dumps.git

diff --git a/onewire/sockit_owm/README b/onewire/sockit_owm/README
index e894f08..c84e364 100644
--- a/onewire/sockit_owm/README
+++ b/onewire/sockit_owm/README
@@ -1,4 +1,34 @@
-sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr
+-------------------------------------------------------------------------------
+Onewire dumps, sockit_owm master
+-------------------------------------------------------------------------------
+
+This directory contains waveforms created by accessing various onewire devices
+using the 'sockit_owm' Verilog master. The master is used in a demo hardware
+(Terasic DE1 development board, and a Quartus/Qsys project) and software (also
+available as a Nios II project) implementation.
+
+Details:
+https://github.com/jeras/sockit_owm
+
+
+Logic analyzer setup
+--------------------
+
+The logic analyzer used was a Saleae Logic (at 8MHz):
+
+  Probe       1-Wire pin
+  ----------------------
+  1 (black)   OWR
+
+
+Data
+----
+
+The sigrok command line used was:
+
+  sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr
+
+This is the console output after running the demo:
 
 (0) 6700000003A6A842  25.9 Celsius
 (1) 3F000000C8CF9B28  25.8 Celsius