X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=lpc%2Fvultureprog%2FREADME;h=3dcdeb5e2fb3996f28ca90cfb54b0fd0b395503d;hb=22548bdf1bf288f4421f0acbb3702408b821b271;hp=5f652e24b0c65ebc13927aac4de6f859d20fdf0c;hpb=f768de429849ee61c60ba6db8f21145faf818736;p=sigrok-dumps.git

diff --git a/lpc/vultureprog/README b/lpc/vultureprog/README
index 5f652e2..3dcdeb5 100644
--- a/lpc/vultureprog/README
+++ b/lpc/vultureprog/README
@@ -2,49 +2,54 @@
 Arbitrary LPC (low pin count) traffic
 -------------------------------------------------------------------------------
 
-These captures are the identification and programming with random data of a LPC
-(low pin count) interface flash chip. The LPC bus is emulated with an ARM
-Cortex-M microcontroller, and does not run at the standard 33MHz clock. Although
-the clock contains significant jitter, the connected chips respond and
-communicate as expected.
+These captures are the identification and programming with random data of an
+LPC (low pin count) interface flash chip. The LPC bus is emulated with an ARM
+Cortex-M microcontroller, and does not run at the standard 33MHz clock.
+Although the clock contains significant jitter, the connected chips respond
+and communicate as expected.
 
 Details:
 http://en.wikipedia.org/wiki/Low_Pin_Count
 http://www.intel.com/design/chipsets/industry/25128901.pdf
 
 
-Hardware Setup
+Hardware setup
 --------------
 
-A VultureProg daughterboard was attached to a TI Stellaris Launcphad board. A
-SST49LF080A flash chip was installed in the PLCC socket. The core clock of the
-CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to capture all
-details of the waveform.
+A VultureProg daughterboard was attached to a TI Stellaris Launchpad board.
+An SST49LF080A flash chip was installed in the PLCC socket. The core clock of
+the CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to
+capture all details of the waveform. The logic analyzer used was connected to
+the "LPC probe" header of the VultureProg daughterboard.
 
 Hardware: http://github.com/mrnuke/vultureprog-hardware
 Firmware + SW: http://git.qiprog.org/
 
-The logic analyzer used was a MCU123 USBee AX Pro clone. It was connected to the
-"LPC probe" header of the VultureProg daughterboard. All captures were run at
-24MHz sampling rate.
-
-Hookup
-------
-P0: LAD0
-P1: LAD1
-P2: LAD2
-P3: LAD3
-P4: LCLK
-P5: #LFRAME
-P6: NC
-P7: NC
+The logic analyzer used was an MCU123 USBee AX Pro clone (at 24MHz):
+
+  Probe  LPC
+  ----------
+  0      LAD0
+  1      LAD1
+  2      LAD2
+  3      LAD3
+  4      LCLK
+  5      LFRAME#
+
 
 Data
 ----
 
-- lpc_vultureprog.sr
-  VultureProg BIOS chip programmer programming random data to a SST49LF080A.
+lpc_vultureprog.sr:
+
+  VultureProg BIOS chip programmer programming random data to an SST49LF080A.
   The bus clock was intentionally reduced to allow capture with an FX2-based
   logic analyzer.
 
+The sigrok command line used was:
+
+  sigrok-cli --driver fx2lafw --config samplerate=24mhz --samples 23552000 \
+             -o <filename>
+
 This data is released into the public domain.
+