X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=i2c%2Fgigabyte_6vle-vxl_i2c%2FREADME;h=654743440ee065fe8a22c71fef191cce2862c535;hb=6030f729389379485ed264fad81e39fce08503b1;hp=75abedd47757ce7a858365256247f653fdd2cd11;hpb=c83a7da3a95d3e9b5ead986ac16e2d5d941ce952;p=sigrok-dumps.git

diff --git a/i2c/gigabyte_6vle-vxl_i2c/README b/i2c/gigabyte_6vle-vxl_i2c/README
index 75abedd..6547434 100644
--- a/i2c/gigabyte_6vle-vxl_i2c/README
+++ b/i2c/gigabyte_6vle-vxl_i2c/README
@@ -22,7 +22,7 @@ http://pdf1.alldatasheet.com/datasheet-pdf/view/90645/ICST/ICS950908.html
 Logic analyzer setup
 --------------------
 
-The logic analyzer used for capturing was a Saleae Logic:
+The logic analyzer used was a Saleae Logic (at 2MHz):
 
   Probe       I2C pin
   -------------------