X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=hw%2Fsainsmart-dds120%2Ffw.c;h=8ddbb376f62d510142f4b1e5bd6c8f6d20dfeafc;hb=0adb2e50fd1c9d763a38dd0094f1ff80a7445771;hp=d67e7c912f2d80f7fd1904a812bc96f2eaccb8f2;hpb=ba63ce8b9aba391c41cde4605ef9b941d4a879b3;p=sigrok-firmware-fx2lafw.git diff --git a/hw/sainsmart-dds120/fw.c b/hw/sainsmart-dds120/fw.c index d67e7c91..8ddbb376 100644 --- a/hw/sainsmart-dds120/fw.c +++ b/hw/sainsmart-dds120/fw.c @@ -24,20 +24,20 @@ #include #include -#define SET_ANALOG_MODE() PA7 = 1 +#define SET_ANALOG_MODE() do { PA7 = 1; } while (0) #define SET_COUPLING(x) set_coupling(x) #define SET_CALIBRATION_PULSE(x) set_calibration_pulse(x) /* Note: There's no PE2 as IOE is not bit-addressable (see TRM 15.2). */ -#define TOGGLE_CALIBRATION_PIN() IOE = IOE ^ 0x04 +#define TOGGLE_CALIBRATION_PIN() do { IOE = IOE ^ 0x04; } while (0) #define LED_CLEAR() NOP #define LED_GREEN() NOP #define LED_RED() NOP -#define TIMER2_VAL 1000 +#define TIMER2_VAL 500 /* CTLx pin index (IFCLK, ADC clock input). */ #define CTL_BIT 2