X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Fsysclk-lwla%2Fprotocol.c;h=ebd2a698fe72ea153d0cf09437923fadb116002f;hb=88b1d4e573480757f08ea4312b15bdccc264d444;hp=75b3806362c573ef2d5535b43416d9fe71e5f287;hpb=6358f0a9568848be734a8a94ad7f510e04a4503f;p=libsigrok.git

diff --git a/hardware/sysclk-lwla/protocol.c b/hardware/sysclk-lwla/protocol.c
index 75b38063..ebd2a698 100644
--- a/hardware/sysclk-lwla/protocol.c
+++ b/hardware/sysclk-lwla/protocol.c
@@ -545,7 +545,7 @@ static int process_sample_data(const struct sr_dev_inst *sdi)
 
 		if (acq->rle == RLE_STATE_DATA) {
 			acq->sample = word & ALL_CHANNELS_MASK;
-			acq->run_len = ((word >> NUM_PROBES) & 1) + 1;
+			acq->run_len = ((word >> NUM_CHANNELS) & 1) + 1;
 			if (word & RLE_FLAG_LEN_FOLLOWS)
 				acq->rle = RLE_STATE_LEN;
 		} else {
@@ -738,6 +738,55 @@ SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
 	return ret;
 }
 
+SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
+{
+	struct dev_context *devc;
+	struct sr_trigger *trigger;
+	struct sr_trigger_stage *stage;
+	struct sr_trigger_match *match;
+	const GSList *l, *m;
+	uint64_t channel_index;
+
+	devc = sdi->priv;
+
+	devc->trigger_mask = 0;
+	devc->trigger_values = 0;
+	devc->trigger_edge_mask = 0;
+
+	if (!(trigger = sr_session_trigger_get()))
+		return SR_OK;
+
+	if (g_slist_length(trigger->stages) > 1) {
+		sr_err("This device only supports 1 trigger stage.");
+		return SR_ERR;
+	}
+
+	for (l = trigger->stages; l; l = l->next) {
+		stage = l->data;
+		for (m = stage->matches; m; m = m->next) {
+			match = m->data;
+			if (!match->channel->enabled)
+				/* Ignore disabled channels with a trigger. */
+				continue;
+			channel_index = 1 << match->channel->index;
+			devc->trigger_mask |= channel_index;
+			switch (match->match) {
+			case SR_TRIGGER_ONE:
+				devc->trigger_values |= channel_index;
+				break;
+			case SR_TRIGGER_RISING:
+				devc->trigger_values |= channel_index;
+				/* Fall through for edge mask. */
+			case SR_TRIGGER_FALLING:
+				devc->trigger_edge_mask |= channel_index;
+				break;
+			}
+		}
+	}
+
+	return SR_OK;
+}
+
 /* Select the LWLA clock configuration.  If the clock source changed from
  * the previous setting, this will download a new bitstream to the FPGA.
  */