X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Frigol-ds%2Fprotocol.c;h=af369e9cf5881234d316c15faa1237b9e9999b3b;hb=81a9ab725f9ce9125c9bc22bc5ebd2903c26bc35;hp=a900872507521fecfe1070a6d6263065988ce1d6;hpb=17b5b202640c1ea5de09b0685a5ed6635f2e06df;p=libsigrok.git

diff --git a/hardware/rigol-ds/protocol.c b/hardware/rigol-ds/protocol.c
index a9008725..af369e9c 100644
--- a/hardware/rigol-ds/protocol.c
+++ b/hardware/rigol-ds/protocol.c
@@ -469,7 +469,10 @@ SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 					len < ACQ_BUFFER_SIZE ? len : ACQ_BUFFER_SIZE);
 		} else {
 			waveform_size = probe->type == SR_PROBE_ANALOG ?
-					DS1000_ANALOG_LIVE_WAVEFORM_SIZE : DIGITAL_WAVEFORM_SIZE;
+					(devc->model->series == RIGOL_VS5000 ?
+						VS5000_ANALOG_LIVE_WAVEFORM_SIZE :
+						DS1000_ANALOG_LIVE_WAVEFORM_SIZE) :
+					DIGITAL_WAVEFORM_SIZE;
 			len = sr_scpi_read(scpi, (char *)devc->buffer,
 					waveform_size - devc->num_frame_bytes);
 		}
@@ -517,19 +520,15 @@ SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
 						rigol_ds_set_wait_event(devc, WAIT_BLOCK);
 				} else
 					sr_dbg("%d of %d block bytes read", devc->num_block_read, devc->num_block_bytes);
+			}
 
-				devc->num_frame_bytes += len;
+			devc->num_frame_bytes += len;
 
-				if (devc->num_frame_bytes < devc->analog_frame_size)
-					/* Don't have the whole frame yet. */
-					return TRUE;
+			if (devc->num_frame_bytes < devc->analog_frame_size)
+				/* Don't have the whole frame yet. */
+				return TRUE;
 
-				sr_dbg("Frame completed, %d samples", devc->num_frame_bytes);
-			} else {
-				if (len != DS1000_ANALOG_LIVE_WAVEFORM_SIZE)
-					/* Don't have the whole frame yet. */
-					return TRUE;
-			}
+			sr_dbg("Frame completed, %d samples", devc->num_frame_bytes);
 		} else {
 			logic.length = len - 10;
 			logic.unitsize = 2;