X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=hardware%2Fasix-sigma%2Fasix-sigma.h;h=4c9deff68bf480ddbf859fe8eb5c3bd747bad115;hb=0acdd79357633e90bb1a398e246ad96b39dceda9;hp=1320acec39eefdc1241abb2bdc8ba2c2b568ff7f;hpb=c53d793f037878992a40c37aa4c0f5f5a3d1c2d8;p=libsigrok.git diff --git a/hardware/asix-sigma/asix-sigma.h b/hardware/asix-sigma/asix-sigma.h index 1320acec..4c9deff6 100644 --- a/hardware/asix-sigma/asix-sigma.h +++ b/hardware/asix-sigma/asix-sigma.h @@ -1,5 +1,5 @@ /* - * This file is part of the sigrok project. + * This file is part of the libsigrok project. * * Copyright (C) 2010 Håvard Espeland , * Copyright (C) 2010 Martin Stensgård @@ -19,8 +19,10 @@ * along with this program. If not, see . */ -#ifndef ASIX_SIGMA_H -#define ASIX_SIGMA_H +#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H +#define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H + +#define LOG_PREFIX "asix-sigma" enum sigma_write_register { WRITE_CLOCK_SELECT = 0, @@ -53,17 +55,17 @@ enum sigma_read_register { READ_TEST = 15, }; -#define REG_ADDR_LOW (0 << 4) -#define REG_ADDR_HIGH (1 << 4) -#define REG_DATA_LOW (2 << 4) -#define REG_DATA_HIGH_WRITE (3 << 4) -#define REG_READ_ADDR (4 << 4) -#define REG_DRAM_WAIT_ACK (5 << 4) +#define REG_ADDR_LOW (0x0 << 4) +#define REG_ADDR_HIGH (0x1 << 4) +#define REG_DATA_LOW (0x2 << 4) +#define REG_DATA_HIGH_WRITE (0x3 << 4) +#define REG_READ_ADDR (0x4 << 4) +#define REG_DRAM_WAIT_ACK (0x5 << 4) /* Bit (1 << 4) can be low or high (double buffer / cache) */ -#define REG_DRAM_BLOCK (6 << 4) -#define REG_DRAM_BLOCK_BEGIN (8 << 4) -#define REG_DRAM_BLOCK_DATA (10 << 4) +#define REG_DRAM_BLOCK (0x6 << 4) +#define REG_DRAM_BLOCK_BEGIN (0x8 << 4) +#define REG_DRAM_BLOCK_DATA (0xa << 4) #define LEDSEL0 6 #define LEDSEL1 7 @@ -74,10 +76,29 @@ enum sigma_read_register { #define CHUNK_SIZE 1024 +/* + * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024]; + */ + +/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */ +struct sigma_dram_cluster { + uint8_t timestamp_lo; + uint8_t timestamp_hi; + struct { + uint8_t sample_hi; + uint8_t sample_lo; + } samples[7]; +}; + +/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */ +struct sigma_dram_line { + struct sigma_dram_cluster cluster[64]; +}; + struct clockselect_50 { uint8_t async; uint8_t fraction; - uint16_t disabled_probes; + uint16_t disabled_channels; }; /* The effect of all these are still a bit unclear. */ @@ -124,18 +145,14 @@ struct triggerlut { /* Trigger configuration */ struct sigma_trigger { - /* Single-pin trigger support (100 and 200 MHz).*/ - uint8_t fast_pin; - uint8_t fast_fall; + /* Only two channels can be used in mask. */ + uint16_t risingmask; + uint16_t fallingmask; /* Simple trigger support (<= 50 MHz). */ uint16_t simplemask; uint16_t simplevalue; - /* Only two probes can be used in mask */ - uint16_t risingmask; - uint16_t fallingmask; - /* TODO: Advanced trigger support (boolean expressions). */ }; @@ -161,4 +178,34 @@ enum triggerfunc { FUNC_NXOR, }; +struct sigma_state { + enum { + SIGMA_UNINITIALIZED = 0, + SIGMA_IDLE, + SIGMA_CAPTURE, + SIGMA_DOWNLOAD, + } state; + + uint16_t lastts; + uint16_t lastsample; +}; + +/* Private, per-device-instance driver context. */ +struct dev_context { + struct ftdi_context ftdic; + uint64_t cur_samplerate; + uint64_t period_ps; + uint64_t limit_msec; + struct timeval start_tv; + int cur_firmware; + int num_channels; + int cur_channels; + int samples_per_event; + int capture_ratio; + struct sigma_trigger trigger; + int use_triggers; + struct sigma_state state; + void *cb_data; +}; + #endif