X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=cdbebebf27e2c2f0ceb8e02beab7afc5f00d538b;hb=c945a82d3217da1a7c651ba2404070e00287c87b;hp=bd2ec575a95aa4e6ca35b303a925426e014c5df3;hpb=2bde58c5654e7f0103a301548ac60ba294d5b649;p=libsigrokdecode.git

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index bd2ec57..cdbebeb 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -71,7 +71,8 @@ class Decoder(srd.Decoder):
     desc     = 'Zilog Z80 microprocessor disassembly.'
     license  = 'gplv3+'
     inputs   = ['logic']
-    outputs  = ['z80']
+    outputs  = []
+    tags     = ['Retro computing']
     channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
@@ -92,15 +93,15 @@ class Decoder(srd.Decoder):
         } for i in range(16)
     )
     annotations = (
-        ('addr',  'Memory or I/O address'),
+        ('addr', 'Memory or I/O address'),
         ('memrd', 'Byte read from memory'),
         ('memwr', 'Byte written to memory'),
-        ('iord',  'Byte read from I/O port'),
-        ('iowr',  'Byte written to I/O port'),
+        ('iord', 'Byte read from I/O port'),
+        ('iowr', 'Byte written to I/O port'),
         ('instr', 'Z80 CPU instruction'),
-        ('rop',   'Value of input operand'),
-        ('wop',   'Value of output operand'),
-        ('warn',  'Warning message'),
+        ('rop', 'Value of input operand'),
+        ('wop', 'Value of output operand'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),
@@ -111,6 +112,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.prev_cycle = Cycle.NONE
         self.op_state   = self.state_IDLE
 
@@ -132,7 +136,7 @@ class Decoder(srd.Decoder):
     def decode(self):
         while True:
             # TODO: Come up with more appropriate self.wait() conditions.
-            pins = self.wait({'skip': 1})
+            pins = self.wait()
             cycle = Cycle.NONE
             if pins[Pin.MREQ] != 1: # default to asserted
                 if pins[Pin.RD] == 0: