X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=df61628befe9d6eda851ffdc5c530e59e27736bc;hb=ab96960eded15c227208e49007a0b3f65c046aa3;hp=05ff3d53ae90901a136350f07d4247230d6f9e71;hpb=d1970f14488ad23f595994779831cd8897c39300;p=libsigrokdecode.git

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 05ff3d5..df61628 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -65,12 +65,18 @@ class Decoder(srd.Decoder):
         'signalling': ['Signalling', 'full-speed'],
     }
     annotations = [
-        ['Text', 'Human-readable text'],
+        ['symbol', 'Symbol'],
+        ['sop', 'Start of packet (SOP)'],
+        ['eop', 'End of packet (EOP)'],
+        ['bit', 'Bit'],
+        ['stuffbit', 'Stuff bit'],
+        ['packet', 'Packet'],
     ]
 
     def __init__(self):
         self.oldsym = 'J' # The "idle" state is J.
-        self.ss_sop = -1
+        self.ss_sop = None
+        self.ss_block = None
         self.samplenum = 0
         self.packet = ''
         self.syms = []
@@ -87,6 +93,7 @@ class Decoder(srd.Decoder):
         self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
         self.bitrate = bitrates[self.options['signalling']]
         self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
+        self.halfbit = int(self.bitwidth / 2)
 
     def report(self):
         pass
@@ -97,13 +104,21 @@ class Decoder(srd.Decoder):
     def putx(self, data):
         self.put(self.samplenum, self.samplenum, self.out_ann, data)
 
+    def putpm(self, data):
+        s, h = self.samplenum, self.halfbit
+        self.put(self.ss_block - h, self.samplenum + h, self.out_proto, data)
+
+    def putm(self, data):
+        s, h = self.samplenum, self.halfbit
+        self.put(self.ss_block - h, self.samplenum + h, self.out_ann, data)
+
     def putpb(self, data):
-        s, halfbit = self.samplenum, int(self.bitwidth / 2)
-        self.put(s - halfbit, s + halfbit, self.out_proto, data)
+        s, h = self.samplenum, self.halfbit
+        self.put(s - h, s + h, self.out_proto, data)
 
     def putb(self, data):
-        s, halfbit = self.samplenum, int(self.bitwidth / 2)
-        self.put(s - halfbit, s + halfbit, self.out_ann, data)
+        s, h = self.samplenum, self.halfbit
+        self.put(s - h, s + h, self.out_ann, data)
 
     def set_new_target_samplenum(self):
         bitpos = self.ss_sop + (self.bitwidth / 2)
@@ -118,17 +133,17 @@ class Decoder(srd.Decoder):
         self.ss_sop = self.samplenum
         self.set_new_target_samplenum()
         self.putpx(['SOP', None])
-        self.putx([0, ['SOP']])
+        self.putx([1, ['SOP']])
         self.state = 'GET BIT'
 
     def handle_bit(self, sym, b):
         if self.consecutive_ones == 6 and b == '0':
             # Stuff bit. Don't add to the packet, reset self.consecutive_ones.
-            self.putb([0, ['SB: %s/%s' % (sym, b)]])
+            self.putb([4, ['SB: %s/%s' % (sym, b)]])
             self.consecutive_ones = 0
         else:
             # Normal bit. Add it to the packet, update self.consecutive_ones.
-            self.putb([0, ['%s/%s' % (sym, b)]])
+            self.putb([3, ['%s/%s' % (sym, b)]])
             self.packet += b
             if b == '1':
                 self.consecutive_ones += 1
@@ -145,8 +160,11 @@ class Decoder(srd.Decoder):
         self.oldsym = sym
         if self.syms[-2:] == ['SE0', 'J']:
             # Got an EOP, i.e. we now have a full packet.
-            self.putpb(['PACKET', self.packet])
-            self.putb([0, ['PACKET: %s' % self.packet]])
+            self.putpm(['EOP', None])
+            self.putm([2, ['EOP']])
+            self.ss_block = self.ss_sop
+            self.putpm(['PACKET', self.packet])
+            self.putm([5, ['PACKET: %s' % self.packet]])
             self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE'
             self.consecutive_ones = 0
 
@@ -154,6 +172,7 @@ class Decoder(srd.Decoder):
         if sym == 'SE0':
             # Start of an EOP. Change state, run get_eop() for this bit.
             self.state = 'GET EOP'
+            self.ss_block = self.samplenum
             self.get_eop(sym)
             return
         self.syms.append(sym)