X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=6b4c02849a3d62fc639c8d64b967eb56b9e776e2;hb=a241cfb6e1fbf1f7c85109a54e914672b633f5f3;hp=543089e041ef76dbbd51b153eed128a792a200c6;hpb=066d659423912025b5b680c5bf74fca11aa72398;p=libsigrokdecode.git diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index 543089e..6b4c028 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -66,8 +66,18 @@ bitrates = { 'full-speed': 12000000, # 12Mb/s (+/- 0.25%) } +sym_idx = { + 'J': 0, + 'K': 1, + 'SE0': 2, + 'SE1': 3, +} + +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'usb_signalling' name = 'USB signalling' longname = 'Universal Serial Bus (LS/FS) signalling' @@ -75,24 +85,27 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['usb_signalling'] - probes = [ + channels = ( {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, - ] - optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } - annotations = [ - ['sym', 'Symbol'], - ['sop', 'Start of packet (SOP)'], - ['eop', 'End of packet (EOP)'], - ['bit', 'Bit'], - ['stuffbit', 'Stuff bit'], - ] + ) + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, + ) + annotations = ( + ('sym-j', 'J symbol'), + ('sym-k', 'K symbol'), + ('sym-se0', 'SE0 symbol'), + ('sym-se1', 'SE1 symbol'), + ('sop', 'Start of packet (SOP)'), + ('eop', 'End of packet (EOP)'), + ('bit', 'Bit'), + ('stuffbit', 'Stuff bit'), + ) annotation_rows = ( - ('bits', 'Bits', (1, 2, 3, 4)), - ('symbols', 'Symbols', (0,)), + ('bits', 'Bits', (4, 5, 6, 7)), + ('symbols', 'Symbols', (0, 1, 2, 3)), ) def __init__(self): @@ -104,9 +117,11 @@ class Decoder(srd.Decoder): self.syms = [] self.bitrate = None self.bitwidth = None - self.bitnum = 0 + self.samplepos = None self.samplenum_target = None + self.samplenum_edge = None self.oldpins = None + self.edgepins = None self.consecutive_ones = 0 self.state = 'IDLE' @@ -137,16 +152,16 @@ class Decoder(srd.Decoder): def putpb(self, data): s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_python, data) + self.put(self.samplenum_edge, s + h, self.out_python, data) def putb(self, data): s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_ann, data) + self.put(self.samplenum_edge, s + h, self.out_ann, data) def set_new_target_samplenum(self): - bitpos = self.ss_sop + (self.bitwidth / 2) - bitpos += self.bitnum * self.bitwidth - self.samplenum_target = int(bitpos) + self.samplepos += self.bitwidth; + self.samplenum_target = int(self.samplepos) + self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2)) def wait_for_sop(self, sym): # Wait for a Start of Packet (SOP), i.e. a J->K symbol change. @@ -154,23 +169,24 @@ class Decoder(srd.Decoder): self.oldsym = sym return self.ss_sop = self.samplenum + self.samplepos = self.ss_sop - (self.bitwidth / 2) + 0.5 self.set_new_target_samplenum() self.putpx(['SOP', None]) - self.putx([1, ['SOP']]) + self.putx([4, ['SOP', 'S']]) self.state = 'GET BIT' def handle_bit(self, sym, b): if self.consecutive_ones == 6 and b == '0': # Stuff bit. self.putpb(['STUFF BIT', None]) - self.putb([4, ['SB: %s' % b]]) - self.putb([0, ['%s' % sym]]) + self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]]) + self.putb([sym_idx[sym], ['%s' % sym]]) self.consecutive_ones = 0 else: # Normal bit (not a stuff bit). self.putpb(['BIT', b]) - self.putb([3, ['%s' % b]]) - self.putb([0, ['%s' % sym]]) + self.putb([6, ['%s' % b]]) + self.putb([sym_idx[sym], ['%s' % sym]]) if b == '1': self.consecutive_ones += 1 else: @@ -180,16 +196,16 @@ class Decoder(srd.Decoder): # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J. self.syms.append(sym) self.putpb(['SYM', sym]) - self.putb([0, ['%s' % sym]]) - self.bitnum += 1 + self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]]) self.set_new_target_samplenum() self.oldsym = sym if self.syms[-2:] == ['SE0', 'J']: # Got an EOP. self.putpm(['EOP', None]) - self.putm([2, ['EOP']]) - self.bitnum, self.syms, self.state = 0, [], 'IDLE' + self.putm([5, ['EOP', 'E']]) + self.syms, self.state = [], 'IDLE' self.consecutive_ones = 0 + self.bitwidth = float(self.samplerate) / float(self.bitrate) def get_bit(self, sym): if sym == 'SE0': @@ -201,14 +217,23 @@ class Decoder(srd.Decoder): self.syms.append(sym) self.putpb(['SYM', sym]) b = '0' if self.oldsym != sym else '1' + if (self.oldsym != sym): + # edge + edgesym = symbols[self.options['signalling']][tuple(self.edgepins)] + if (edgesym not in ('SE0', 'SE1')): + if (edgesym == sym): + self.bitwidth = self.bitwidth - (0.001 * self.bitwidth) + self.samplepos = self.samplepos - (0.01 * self.bitwidth) + else: + self.bitwidth = self.bitwidth + (0.001 * self.bitwidth) + self.samplepos = self.samplepos + (0.01 * self.bitwidth) self.handle_bit(sym, b) - self.bitnum += 1 self.set_new_target_samplenum() self.oldsym = sym def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') for (self.samplenum, pins) in data: # State machine. if self.state == 'IDLE': @@ -218,8 +243,11 @@ class Decoder(srd.Decoder): self.oldpins = pins sym = symbols[self.options['signalling']][tuple(pins)] self.wait_for_sop(sym) + self.edgepins = pins elif self.state in ('GET BIT', 'GET EOP'): # Wait until we're in the middle of the desired bit. + if self.samplenum == self.samplenum_edge: + self.edgepins = pins if self.samplenum < self.samplenum_target: continue sym = symbols[self.options['signalling']][tuple(pins)] @@ -227,6 +255,3 @@ class Decoder(srd.Decoder): self.get_bit(sym) elif self.state == 'GET EOP': self.get_eop(sym) - else: - raise Exception('Invalid state: %s' % self.state) -