X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=373103614fadf7538d9351f8da0ff478b372f793;hb=6cbba91f23b9f9ace75b4722c9c0776b9211008d;hp=c0e0141d7dcfd5554d3b10ece73180b3278ed968;hpb=12c567037d3bb4b52e5553397c2f9aef6859b840;p=libsigrokdecode.git

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index c0e0141..3731036 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -104,10 +104,11 @@ class Decoder(srd.Decoder):
     id = 'usb_signalling'
     name = 'USB signalling'
     longname = 'Universal Serial Bus (LS/FS) signalling'
-    desc = 'USB (low-speed and full-speed) signalling protocol.'
+    desc = 'USB (low-speed/full-speed) signalling protocol.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb_signalling']
+    tags = ['PC']
     channels = (
         {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
@@ -135,6 +136,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.oldsym = 'J' # The "idle" state is J.
         self.ss_block = None
@@ -190,7 +194,7 @@ class Decoder(srd.Decoder):
         self.put(s, e, self.out_ann, data)
 
     def set_new_target_samplenum(self):
-        self.samplepos += self.bitwidth;
+        self.samplepos += self.bitwidth
         self.samplenum_target = int(self.samplepos)
         self.samplenum_lastedge = self.samplenum_edge
         self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
@@ -302,7 +306,7 @@ class Decoder(srd.Decoder):
             raise SamplerateError('Cannot decode without samplerate.')
 
         # Seed internal state from the very first sample.
-        pins = self.wait({'skip': 1})
+        pins = self.wait()
         sym = symbols[self.options['signalling']][pins]
         self.handle_idle(sym)
 
@@ -329,9 +333,10 @@ class Decoder(srd.Decoder):
                 elif self.state == 'GET EOP':
                     self.get_eop(sym)
             elif self.state == 'WAIT IDLE':
-                pins = self.wait({'skip': 1})
-                if pins == (0, 0):
-                    continue
+                # Skip "all-low" input. Wait for high level on either DP or DM.
+                pins = self.wait()
+                while not pins[0] and not pins[1]:
+                    pins = self.wait([{0: 'h'}, {1: 'h'}])
                 if self.samplenum - self.samplenum_lastedge > 1:
                     sym = symbols[self.options['signalling']][pins]
                     self.handle_idle(sym)