X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fusb%2Fusb.py;h=641ffe0b28a3695d85118f367daf792c6e34b9a8;hb=c2937021535a0ef11f2905e47447da3b589c65e3;hp=99dd4b5addba0225441bbe84207a4ffe2cd83bdf;hpb=156509ca42f0df2380c9f205f9aad337e1a07802;p=libsigrokdecode.git

diff --git a/decoders/usb/usb.py b/decoders/usb/usb.py
index 99dd4b5..641ffe0 100644
--- a/decoders/usb/usb.py
+++ b/decoders/usb/usb.py
@@ -18,22 +18,21 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# USB (full-speed) protocol decoder
+# USB (low-speed and full-speed) protocol decoder
 
 import sigrokdecode as srd
 
-# States
-SE0, J, K, SE1 = 0, 1, 2, 3
-
-# ...
+# Full-speed symbols (used as states of our state machine, too).
+# Note: Low-speed J and K are inverted compared to the full-speed J and K!
 syms = {
-        (0, 0): SE0,
-        (1, 0): J,
-        (0, 1): K,
-        (1, 1): SE1,
+        # (<dp>, <dm>): <symbol/state>
+        (0, 0): 'SE0',
+        (1, 0): 'J',
+        (0, 1): 'K',
+        (1, 1): 'SE1',
 }
 
-# ...
+# Packet IDs
 pids = {
     '10000111': 'OUT',      # Tokens
     '10010110': 'IN',
@@ -47,6 +46,19 @@ pids = {
     '01101001': 'NYET',
 }
 
+def get_sym(signalling, dp, dm):
+    # Note: Low-speed J and K are inverted compared to the full-speed J and K!
+    if signalling == 'low-speed':
+        s = syms[dp, dm]
+        if s == 'J':
+            return 'K'
+        elif s == 'K':
+            return 'J'
+        else:
+            return s
+    elif signalling == 'full-speed':
+       return syms[dp, dm]
+
 def bitstr_to_num(bitstr):
     if not bitstr:
         return 0
@@ -68,7 +80,6 @@ def packet_decode(packet):
             dev = bitstr_to_num(data[:7])
             ep = bitstr_to_num(data[7:])
             data = 'DEV %d EP %d' % (dev, ep)
-
     elif pid in ('DATA0', 'DATA1'):
         data = packet[16:-16]
         tmp = ''
@@ -79,6 +90,7 @@ def packet_decode(packet):
     else:
         data = packet[16:]
 
+    # The SYNC pattern for low-speed/full-speed is KJKJKJKK (0001).
     if sync != '00000001':
         return 'SYNC INVALID!'
 
@@ -88,9 +100,8 @@ class Decoder(srd.Decoder):
     api_version = 1
     id = 'usb'
     name = 'USB'
-    longname = 'Universal Serial Bus'
-    desc = 'Universal Serial Bus'
-    longdesc = '...longdesc...'
+    longname = 'Universal Serial Bus (LS/FS)'
+    desc = 'USB 1.x (low-speed and full-speed) serial protocol.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb']
@@ -99,57 +110,60 @@ class Decoder(srd.Decoder):
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
     ]
     optional_probes = []
-    options = {}
+    options = {
+        'signalling': ['Signalling', 'full-speed'],
+    }
     annotations = [
-        ['TODO', 'TODO']
+        ['Text', 'Human-readable text']
     ]
 
     def __init__(self):
-        pass
+        self.sym = 'J'
+        self.samplenum = 0
+        self.scount = 0
+        self.packet = ''
 
     def start(self, metadata):
-        self.rate = metadata['samplerate']
+        self.samplerate = metadata['samplerate']
 
         # self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
 
-        if self.rate < 48000000:
-            raise Exception('Sample rate (%d) not sufficient for USB '
-                            'decoding, need at least 48MHz' % self.rate)
-
-        # Initialise decoder state.
-        self.sym = J
-        self.scount = 0
-        self.packet = ''
-
     def report(self):
         pass
 
     def decode(self, ss, es, data):
-        for (samplenum, (dm, dp)) in data:
+        for (self.samplenum, (dp, dm)) in data:
 
+            # Note: self.samplenum is the absolute sample number, whereas
+            # self.scount only counts the number of samples since the
+            # last change in the D+/D- lines.
             self.scount += 1
 
-            sym = syms[dp, dm]
+            sym = get_sym(self.options['signalling'], dp, dm)
 
-            # ...
+            # Wait for a symbol change (i.e., change in D+/D- lines).
             if sym == self.sym:
                 continue
 
             if self.scount == 1:
-                # We ignore single sample width pulses.
-                # I sometimes get these with the OLS.
+                # We ignore single sample width "pulses", i.e., symbol changes
+                # (D+/D- line changes). I sometimes get these with the OLS.
                 self.sym = sym
                 self.scount = 0
                 continue
 
             # How many bits since the last transition?
-            if self.packet != '' or self.sym != J:
-                bitcount = int((self.scount - 1) * 12000000 / self.rate)
+            if self.packet != '' or self.sym != 'J':
+                if self.options['signalling'] == 'low-speed':
+                    bitrate = 1500000 # 1.5Mb/s (+/- 1.5%)
+                elif self.options['signalling'] == 'full-speed':
+                    bitrate = 12000000 # 12Mb/s (+/- 0.25%)
+                bitcount = int((self.scount - 1) * bitrate / self.samplerate)
             else:
                 bitcount = 0
 
-            if self.sym == SE0:
+            if self.sym == 'SE0':
                 if bitcount == 1:
                     # End-Of-Packet (EOP)
                     self.put(0, 0, self.out_ann,
@@ -166,7 +180,7 @@ class Decoder(srd.Decoder):
             self.packet += '1' * bitcount
 
             # Handle bit stuffing.
-            if bitcount < 6 and sym != SE0:
+            if bitcount < 6 and sym != 'SE0':
                 self.packet += '0'
             elif bitcount > 6:
                 self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']])