X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart.py;h=eec3908040a7683f0e567d97f92b20aca5486f99;hb=526e580446dd45c3cb6811dd69a31eaff54e908e;hp=9243bbc3e33741e38ec09e033dd88258aa5bb3a3;hpb=eb7082c98efad727d88e3ebeadcd496fa948475b;p=libsigrokdecode.git

diff --git a/decoders/uart.py b/decoders/uart.py
index 9243bbc..eec3908 100644
--- a/decoders/uart.py
+++ b/decoders/uart.py
@@ -193,7 +193,7 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
 class Decoder(srd.Decoder):
     id = 'uart'
     name = 'UART'
-    longname = 'Universal Asynchronous Receiver/Transmitter (UART)'
+    longname = 'Universal Asynchronous Receiver/Transmitter'
     desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
     longdesc = 'TODO.'
     author = 'Uwe Hermann'
@@ -215,7 +215,6 @@ class Decoder(srd.Decoder):
         'num_stop_bits': ['Stop bit(s)', STOP_BITS_1],
         'bit_order': ['Bit order', LSB_FIRST],
         # TODO: Options to invert the signal(s).
-        # ...
     }
     annotations = [
         # ANN_ASCII
@@ -231,14 +230,6 @@ class Decoder(srd.Decoder):
     ]
 
     def __init__(self, **kwargs):
-        # Set defaults, can be overridden in 'start'.
-        self.baudrate = 115200
-        self.num_data_bits = 8
-        self.parity = PARITY_NONE
-        self.check_parity = True
-        self.num_stop_bits = 1
-        self.bit_order = LSB_FIRST
-
         self.samplenum = 0
         self.frame_start = -1
         self.startbit = -1
@@ -253,18 +244,20 @@ class Decoder(srd.Decoder):
         self.oldrx = None
         self.oldtx = None
 
+        # Set protocol decoder option defaults.
+        self.baudrate = Decoder.options['baudrate'][1]
+        self.num_data_bits = Decoder.options['num_data_bits'][1]
+        self.parity = Decoder.options['parity'][1]
+        self.check_parity = Decoder.options['parity_check'][1]
+        self.num_stop_bits = Decoder.options['num_stop_bits'][1]
+        self.bit_order = Decoder.options['bit_order'][1]
+
     def start(self, metadata):
         self.samplerate = metadata['samplerate']
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart')
         self.out_ann = self.add(srd.OUTPUT_ANN, 'uart')
 
-        # TODO
-        ### self.baudrate = metadata['baudrate']
-        ### self.num_data_bits = metadata['num_data_bits']
-        ### self.parity = metadata['parity']
-        ### self.parity_check = metadata['parity_check']
-        ### self.num_stop_bits = metadata['num_stop_bits']
-        ### self.bit_order = metadata['bit_order']
+        # TODO: Override PD options, if user wants that.
 
         # The width of one UART bit in number of samples.
         self.bit_width = float(self.samplerate) / float(self.baudrate)
@@ -416,9 +409,9 @@ class Decoder(srd.Decoder):
         self.put(self.samplenum, self.samplenum, self.out_ann,
                  [ANN_ASCII, ['Stop bit', 'Stop', 'P']])
 
-    def decode(self, timeoffset, duration, data): # TODO
+    def decode(self, ss, es, data): # TODO
         # for (samplenum, (rx, tx)) in data:
-        for (samplenum, (rx,)) in data:
+        for (samplenum, (rx)) in data:
 
             # TODO: Start counting at 0 or 1? Increase before or after?
             self.samplenum += 1
@@ -448,8 +441,3 @@ class Decoder(srd.Decoder):
             self.oldrx = rx
             # self.oldtx = tx
 
-        # if proto != []:
-        #     self.put(0, 0, self.out_proto, proto)
-        # if ann != []:
-        #     self.put(0, 0, self.out_ann, ann)
-