X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=a478c8eb7906019ea21fcb5c35e57683420f6162;hb=e5edf39f10053515fb044314adf83820ad118c57;hp=057a8900811f94503895c36247d5e66a9639455e;hpb=1541976fcac03a780b5d27046f5f8884973c08ae;p=libsigrokdecode.git

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 057a890..a478c8e 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -62,7 +62,6 @@ class Decoder(srd.Decoder):
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
     desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
-    longdesc = 'TODO.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
@@ -266,10 +265,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either RX or TX could be omitted (optional probe).
-        for (samplenum, (rx, tx)) in data:
-
-            # TODO: Start counting at 0 or 1? Increase before or after?
-            self.samplenum += 1
+        for (self.samplenum, (rx, tx)) in data:
 
             # First sample: Save RX/TX value.
             if self.oldbit[RX] == None: