X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=a478c8eb7906019ea21fcb5c35e57683420f6162;hb=4180cba9a51acd32f69f0f8628bb746ea3e12be6;hp=2bb61dd86ca546ad119360fedc589626f4f4ff85;hpb=2b7160383cc189f721600c04be17a980e216dfd6;p=libsigrokdecode.git

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 2bb61dd..a478c8e 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -62,7 +62,6 @@ class Decoder(srd.Decoder):
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
     desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
-    longdesc = 'TODO.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
@@ -102,10 +101,7 @@ class Decoder(srd.Decoder):
         self.paritybit = [-1, -1]
         self.stopbit1 = [-1, -1]
         self.startsample = [-1, -1]
-
-        # Initial state.
         self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
-
         self.oldbit = [None, None]
 
     def start(self, metadata):
@@ -269,10 +265,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either RX or TX could be omitted (optional probe).
-        for (samplenum, (rx, tx)) in data:
-
-            # TODO: Start counting at 0 or 1? Increase before or after?
-            self.samplenum += 1
+        for (self.samplenum, (rx, tx)) in data:
 
             # First sample: Save RX/TX value.
             if self.oldbit[RX] == None: