X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=24551da6d03e177854e289178173512fa8704b98;hb=92d1aba34bbe661b388e874fda0a41f477d3e30d;hp=4ceaef6423cb14a75a765382173a50dbe11df48c;hpb=8e828d2a29154fb9cae8c9c38d27c60f820dd584;p=libsigrokdecode.git diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py index 4ceaef6..24551da 100644 --- a/decoders/uart/uart.py +++ b/decoders/uart/uart.py @@ -18,40 +18,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# # UART protocol decoder -# import sigrokdecode as srd -# States -WAIT_FOR_START_BIT = 0 -GET_START_BIT = 1 -GET_DATA_BITS = 2 -GET_PARITY_BIT = 3 -GET_STOP_BITS = 4 - # Used for differentiating between the two data directions. RX = 0 TX = 1 -# Parity options -PARITY_NONE = 0 -PARITY_ODD = 1 -PARITY_EVEN = 2 -PARITY_ZERO = 3 -PARITY_ONE = 4 - -# Stop bit options -STOP_BITS_0_5 = 0 -STOP_BITS_1 = 1 -STOP_BITS_1_5 = 2 -STOP_BITS_2 = 3 - -# Bit order options -LSB_FIRST = 0 -MSB_FIRST = 1 - # Annotation feed formats ANN_ASCII = 0 ANN_DEC = 1 @@ -62,22 +36,22 @@ ANN_BITS = 4 # Given a parity type to check (odd, even, zero, one), the value of the # parity bit, the value of the data, and the length of the data (5-9 bits, # usually 8 bits) return True if the parity is correct, False otherwise. -# PARITY_NONE is _not_ allowed as value for 'parity_type'. +# 'none' is _not_ allowed as value for 'parity_type'. def parity_ok(parity_type, parity_bit, data, num_data_bits): # Handle easy cases first (parity bit is always 1 or 0). - if parity_type == PARITY_ZERO: + if parity_type == 'zero': return parity_bit == 0 - elif parity_type == PARITY_ONE: + elif parity_type == 'one': return parity_bit == 1 # Count number of 1 (high) bits in the data (and the parity bit itself!). ones = bin(data).count('1') + parity_bit # Check for odd/even parity. - if parity_type == PARITY_ODD: + if parity_type == 'odd': return (ones % 2) == 1 - elif parity_type == PARITY_EVEN: + elif parity_type == 'even': return (ones % 2) == 0 else: raise Exception('Invalid parity type: %d' % parity_type) @@ -87,8 +61,7 @@ class Decoder(srd.Decoder): id = 'uart' name = 'UART' longname = 'Universal Asynchronous Receiver/Transmitter' - desc = 'Universal Asynchronous Receiver/Transmitter (UART)' - longdesc = 'TODO.' + desc = 'Asynchronous, serial bus.' license = 'gplv2+' inputs = ['logic'] outputs = ['uart'] @@ -102,10 +75,10 @@ class Decoder(srd.Decoder): options = { 'baudrate': ['Baud rate', 115200], 'num_data_bits': ['Data bits', 8], # Valid: 5-9. - 'parity_type': ['Parity type', PARITY_NONE], - 'parity_check': ['Check parity?', True], # TODO: Bool supported? - 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1], - 'bit_order': ['Bit order', LSB_FIRST], + 'parity_type': ['Parity type', 'none'], + 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported? + 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5. + 'bit_order': ['Bit order', 'lsb-first'], # TODO: Options to invert the signal(s). } annotations = [ @@ -128,11 +101,9 @@ class Decoder(srd.Decoder): self.paritybit = [-1, -1] self.stopbit1 = [-1, -1] self.startsample = [-1, -1] - - # Initial state. - self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT] - + self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] self.oldbit = [None, None] + self.oldpins = None def start(self, metadata): self.samplerate = metadata['samplerate'] @@ -172,7 +143,7 @@ class Decoder(srd.Decoder): # Save the sample number where the start bit begins. self.frame_start[rxtx] = self.samplenum - self.state[rxtx] = GET_START_BIT + self.state[rxtx] = 'GET START BIT' def get_start_bit(self, rxtx, signal): # Skip samples until we're in the middle of the start bit. @@ -191,7 +162,7 @@ class Decoder(srd.Decoder): self.databyte[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = GET_DATA_BITS + self.state[rxtx] = 'GET DATA BITS' self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, ['STARTBIT', rxtx, self.startbit[rxtx]]) @@ -208,15 +179,15 @@ class Decoder(srd.Decoder): self.startsample[rxtx] = self.samplenum # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == LSB_FIRST: + if self.options['bit_order'] == 'lsb-first': self.databyte[rxtx] >>= 1 self.databyte[rxtx] |= \ (signal << (self.options['num_data_bits'] - 1)) - elif self.options['bit_order'] == MSB_FIRST: + elif self.options['bit_order'] == 'msb-first': self.databyte[rxtx] <<= 1 self.databyte[rxtx] |= (signal << 0) else: - raise Exception('Invalid bit order value: %d', + raise Exception('Invalid bit order value: %s', self.options['bit_order']) # Return here, unless we already received all data bits. @@ -225,7 +196,7 @@ class Decoder(srd.Decoder): self.cur_data_bit[rxtx] += 1 return - self.state[rxtx] = GET_PARITY_BIT + self.state[rxtx] = 'GET PARITY BIT' self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto, ['DATA', rxtx, self.databyte[rxtx]]) @@ -242,8 +213,8 @@ class Decoder(srd.Decoder): def get_parity_bit(self, rxtx, signal): # If no parity is used/configured, skip to the next state immediately. - if self.options['parity_type'] == PARITY_NONE: - self.state[rxtx] = GET_STOP_BITS + if self.options['parity_type'] == 'none': + self.state[rxtx] = 'GET STOP BITS' return # Skip samples until we're in the middle of the parity bit. @@ -252,7 +223,7 @@ class Decoder(srd.Decoder): self.paritybit[rxtx] = signal - self.state[rxtx] = GET_STOP_BITS + self.state[rxtx] = 'GET STOP BITS' if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.databyte[rxtx], self.options['num_data_bits']): @@ -272,7 +243,7 @@ class Decoder(srd.Decoder): # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity_type'] == PARITY_NONE else 1 + skip_parity = 0 if self.options['parity_type'] == 'none' else 1 b = self.options['num_data_bits'] + 1 + skip_parity if not self.reached_bit(rxtx, b): return @@ -285,7 +256,7 @@ class Decoder(srd.Decoder): ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) # TODO: Abort? Ignore the frame? Other? - self.state[rxtx] = WAIT_FOR_START_BIT + self.state[rxtx] = 'WAIT FOR START BIT' # TODO: Fix range. self.put(self.samplenum, self.samplenum, self.out_proto, @@ -295,10 +266,13 @@ class Decoder(srd.Decoder): def decode(self, ss, es, data): # TODO: Either RX or TX could be omitted (optional probe). - for (samplenum, (rx, tx)) in data: + for (self.samplenum, pins) in data: - # TODO: Start counting at 0 or 1? Increase before or after? - self.samplenum += 1 + # Note: Ignoring identical samples here for performance reasons + # is not possible for this PD, at least not in the current state. + # if self.oldpins == pins: + # continue + self.oldpins, (rx, tx) = pins, pins # First sample: Save RX/TX value. if self.oldbit[RX] == None: @@ -312,15 +286,15 @@ class Decoder(srd.Decoder): for rxtx in (RX, TX): signal = rx if (rxtx == RX) else tx - if self.state[rxtx] == WAIT_FOR_START_BIT: + if self.state[rxtx] == 'WAIT FOR START BIT': self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) - elif self.state[rxtx] == GET_START_BIT: + elif self.state[rxtx] == 'GET START BIT': self.get_start_bit(rxtx, signal) - elif self.state[rxtx] == GET_DATA_BITS: + elif self.state[rxtx] == 'GET DATA BITS': self.get_data_bits(rxtx, signal) - elif self.state[rxtx] == GET_PARITY_BIT: + elif self.state[rxtx] == 'GET PARITY BIT': self.get_parity_bit(rxtx, signal) - elif self.state[rxtx] == GET_STOP_BITS: + elif self.state[rxtx] == 'GET STOP BITS': self.get_stop_bits(rxtx, signal) else: raise Exception('Invalid state: %d' % self.state[rxtx])