X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=ffacad9acfb6c83c65058b59a4cbda159d6a2b01;hb=15a60d37d4ea14c460068ce4c0e6befdb918692f;hp=6a0dff9dfc8f36bc7d893c5e441ea5d4e57bd880;hpb=080b528200abe354412aba63ddee5d76ac9c8e14;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 6a0dff9..ffacad9 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -18,6 +18,7 @@ ## import sigrokdecode as srd +from common.srdhelper import bitpack from math import floor, ceil ''' @@ -123,14 +124,18 @@ class Decoder(srd.Decoder): ('tx-warnings', 'TX warnings'), ('rx-data-bits', 'RX data bits'), ('tx-data-bits', 'TX data bits'), + ('rx-break', 'RX break'), + ('tx-break', 'TX break'), ) annotation_rows = ( ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), ('rx-warnings', 'RX warnings', (10,)), + ('rx-break', 'RX break', (14,)), ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-data-bits', 'TX bits', (13,)), ('tx-warnings', 'TX warnings', (11,)), + ('tx-break', 'TX break', (15,)), ) binary = ( ('rx', 'RX dump'), @@ -155,11 +160,20 @@ class Decoder(srd.Decoder): s, halfbit = self.samplenum, self.bit_width / 2.0 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) + def putgse(self, ss, es, data): + self.put(ss, es, self.out_ann, data) + + def putpse(self, ss, es, data): + self.put(ss, es, self.out_python, data) + def putbin(self, rxtx, data): s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] @@ -171,6 +185,7 @@ class Decoder(srd.Decoder): self.startsample = [-1, -1] self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] self.databits = [[], []] + self.break_start = [None, None] def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -185,7 +200,7 @@ class Decoder(srd.Decoder): self.bit_width = float(self.samplerate) / float(self.options['baudrate']) def get_sample_point(self, rxtx, bitnum): - """Determine absolute sample number of a bit slot's sample point.""" + # Determine absolute sample number of a bit slot's sample point. # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). @@ -216,25 +231,16 @@ class Decoder(srd.Decoder): self.datavalue[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = 'GET DATA BITS' - self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) + self.state[rxtx] = 'GET DATA BITS' + def get_data_bits(self, rxtx, signal): # Save the sample number of the middle of the first data bit. if self.startsample[rxtx] == -1: self.startsample[rxtx] = self.samplenum - # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == 'lsb-first': - self.datavalue[rxtx] >>= 1 - self.datavalue[rxtx] |= \ - (signal << (self.options['num_data_bits'] - 1)) - else: - self.datavalue[rxtx] <<= 1 - self.datavalue[rxtx] |= (signal << 0) - self.putg([rxtx + 12, ['%d' % signal]]) # Store individual data bits and their start/end samplenumbers. @@ -246,12 +252,11 @@ class Decoder(srd.Decoder): if self.cur_data_bit[rxtx] < self.options['num_data_bits']: return - # Skip to either reception of the parity bit, or reception of - # the STOP bits if parity is not applicable. - self.state[rxtx] = 'GET PARITY BIT' - if self.options['parity_type'] == 'none': - self.state[rxtx] = 'GET STOP BITS' - + # Convert accumulated data bits to a data value. + bits = [b[0] for b in self.databits[rxtx]] + if self.options['bit_order'] == 'msb-first': + bits.reverse() + self.datavalue[rxtx] = bitpack(bits) self.putpx(rxtx, ['DATA', rxtx, (self.datavalue[rxtx], self.databits[rxtx])]) @@ -266,6 +271,12 @@ class Decoder(srd.Decoder): self.databits[rxtx] = [] + # Advance to either reception of the parity bit, or reception of + # the STOP bits if parity is not applicable. + self.state[rxtx] = 'GET PARITY BIT' + if self.options['parity_type'] == 'none': + self.state[rxtx] = 'GET STOP BITS' + def format_value(self, v): # Format value 'v' according to configured options. # Reflects the user selected kind of representation, as well as @@ -311,8 +322,6 @@ class Decoder(srd.Decoder): def get_parity_bit(self, rxtx, signal): self.paritybit[rxtx] = signal - self.state[rxtx] = 'GET STOP BITS' - if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.datavalue[rxtx], self.options['num_data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) @@ -322,6 +331,8 @@ class Decoder(srd.Decoder): self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) + self.state[rxtx] = 'GET STOP BITS' + # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): self.stopbit1[rxtx] = signal @@ -332,20 +343,22 @@ class Decoder(srd.Decoder): self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) # TODO: Abort? Ignore the frame? Other? - self.state[rxtx] = 'WAIT FOR START BIT' - self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) - def get_wait_cond(self, rxtx, inv): - """ - Determine Decoder.wait() condition for specified UART line. + self.state[rxtx] = 'WAIT FOR START BIT' - Returns condititions that are suitable for Decoder.wait(). Those - conditions either match the falling edge of the START bit, or - the sample point of the next bit time. - """ + def handle_break(self, rxtx): + self.putpse(self.frame_start[rxtx], self.samplenum, + ['BREAK', rxtx, 0]) + self.putgse(self.frame_start[rxtx], self.samplenum, + [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']]) + self.state[rxtx] = 'WAIT FOR START BIT' + def get_wait_cond(self, rxtx, inv): + # Return condititions that are suitable for Decoder.wait(). Those + # conditions either match the falling edge of the START bit, or + # the sample point of the next bit time. state = self.state[rxtx] if state == 'WAIT FOR START BIT': return {rxtx: 'r' if inv else 'f'} @@ -358,15 +371,11 @@ class Decoder(srd.Decoder): elif state == 'GET STOP BITS': bitnum = 1 + self.options['num_data_bits'] bitnum += 0 if self.options['parity_type'] == 'none' else 1 - want_num = self.get_sample_point(rxtx, bitnum) - # want_num = int(want_num + 0.5) - want_num = ceil(want_num) - cond = {'skip': want_num - self.samplenum} - return cond + want_num = ceil(self.get_sample_point(rxtx, bitnum)) + return {'skip': want_num - self.samplenum} def inspect_sample(self, rxtx, signal, inv): - """Inspect a sample returned by .wait() for the specified UART line.""" - + # Inspect a sample returned by .wait() for the specified UART line. if inv: signal = not signal @@ -382,6 +391,22 @@ class Decoder(srd.Decoder): elif state == 'GET STOP BITS': self.get_stop_bits(rxtx, signal) + def inspect_edge(self, rxtx, signal, inv): + # Inspect edges, independently from traffic, to detect break conditions. + if inv: + signal = not signal + if not signal: + # Signal went low. Start another interval. + self.break_start[rxtx] = self.samplenum + return + # Signal went high. Was there an extended period with low signal? + if self.break_start[rxtx] is None: + return + diff = self.samplenum - self.break_start[rxtx] + if diff >= self.break_min_sample_count: + self.handle_break(rxtx) + self.break_start[rxtx] = None + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') @@ -392,18 +417,36 @@ class Decoder(srd.Decoder): opt = self.options inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] - cond_idx = [None] * len(has_pin) + cond_data_idx = [None] * len(has_pin) + + # Determine the number of samples for a complete frame's time span. + # A period of low signal (at least) that long is a break condition. + frame_samples = 1 # START + frame_samples += self.options['num_data_bits'] + frame_samples += 0 if self.options['parity_type'] == 'none' else 1 + frame_samples += self.options['num_stop_bits'] + frame_samples *= self.bit_width + self.break_min_sample_count = ceil(frame_samples) + cond_edge_idx = [None] * len(has_pin) while True: conds = [] if has_pin[RX]: - cond_idx[RX] = len(conds) + cond_data_idx[RX] = len(conds) conds.append(self.get_wait_cond(RX, inv[RX])) + cond_edge_idx[RX] = len(conds) + conds.append({RX: 'e'}) if has_pin[TX]: - cond_idx[TX] = len(conds) + cond_data_idx[TX] = len(conds) conds.append(self.get_wait_cond(TX, inv[TX])) + cond_edge_idx[TX] = len(conds) + conds.append({TX: 'e'}) (rx, tx) = self.wait(conds) - if cond_idx[RX] is not None and self.matched[cond_idx[RX]]: + if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]: self.inspect_sample(RX, rx, inv[RX]) - if cond_idx[TX] is not None and self.matched[cond_idx[TX]]: + if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]: + self.inspect_edge(RX, rx, inv[RX]) + if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]: self.inspect_sample(TX, tx, inv[TX]) + if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]: + self.inspect_edge(TX, tx, inv[TX])