X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=fef3aa525fe3b0f32893a8a915cd6cd1b4e24bcd;hb=83df730dd21ce52670a593455cfe5e732989a90d;hp=da5e3033b3023cce80f8416ac96b580815d80eb0;hpb=21cda9512f29947617da45822ab524b1f76f56c1;p=libsigrokdecode.git

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index da5e303..fef3aa5 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -66,8 +66,6 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
         return (ones % 2) == 1
     elif parity_type == 'even':
         return (ones % 2) == 0
-    else:
-        raise Exception('Invalid parity type: %d' % parity_type)
 
 class SamplerateError(Exception):
     pass
@@ -175,7 +173,7 @@ class Decoder(srd.Decoder):
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
-            self.samplerate = value;
+            self.samplerate = value
             # The width of one UART bit in number of samples.
             self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
 
@@ -242,12 +240,9 @@ class Decoder(srd.Decoder):
             self.databyte[rxtx] >>= 1
             self.databyte[rxtx] |= \
                 (signal << (self.options['num_data_bits'] - 1))
-        elif self.options['bit_order'] == 'msb-first':
+        else:
             self.databyte[rxtx] <<= 1
             self.databyte[rxtx] |= (signal << 0)
-        else:
-            raise Exception('Invalid bit order value: %s',
-                            self.options['bit_order'])
 
         self.putg([rxtx + 12, ['%d' % signal]])
 
@@ -277,8 +272,6 @@ class Decoder(srd.Decoder):
             self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
         elif f == 'bin':
             self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
-        else:
-            raise Exception('Invalid data format option: %s' % f)
 
         self.putbin(rxtx, (rxtx, bytes([b])))
         self.putbin(rxtx, (2, bytes([b])))
@@ -366,4 +359,3 @@ class Decoder(srd.Decoder):
 
                 # Save current RX/TX values for the next round.
                 self.oldbit[rxtx] = signal
-