X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=b8508a72c74b7338e7a1039ce6e265e84badda2c;hb=95d11271b46a46788d497481d03177e883c8554e;hp=f01cacece3e86b18274432a0ba1e4d87a7b0e4f2;hpb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index f01cace..b8508a7 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -23,10 +23,10 @@ import sigrokdecode as srd ''' OUTPUT_PYTHON format: -UART packet: -[, , ] +Packet: +[, , ] -This is the list of s and their respective : +This is the list of s and their respective values: - 'STARTBIT': The data is the (integer) value of the start bit (0/1). - 'DATA': The data is the (integer) value of the UART data. Valid values range from 0 to 512 (as the data can be up to 9 bits in size). @@ -66,11 +66,15 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits): return (ones % 2) == 1 elif parity_type == 'even': return (ones % 2) == 0 - else: - raise Exception('Invalid parity type: %d' % parity_type) + +class SamplerateError(Exception): + pass + +class ChannelError(Exception): + pass class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'uart' name = 'UART' longname = 'Universal Asynchronous Receiver/Transmitter' @@ -78,13 +82,12 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['uart'] - probes = [] - optional_probes = [ + optional_channels = ( # Allow specifying only one of the signals, e.g. if only one data # direction exists (or is relevant). {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, - ] + ) options = ( {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, @@ -99,24 +102,27 @@ class Decoder(srd.Decoder): 'values': ('lsb-first', 'msb-first')}, {'id': 'format', 'desc': 'Data format', 'default': 'ascii', 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, - # TODO: Options to invert the signal(s). + {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no', + 'values': ('yes', 'no')}, + {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', + 'values': ('yes', 'no')}, + ) + annotations = ( + ('rx-data', 'RX data'), + ('tx-data', 'TX data'), + ('rx-start', 'RX start bits'), + ('tx-start', 'TX start bits'), + ('rx-parity-ok', 'RX parity OK bits'), + ('tx-parity-ok', 'TX parity OK bits'), + ('rx-parity-err', 'RX parity error bits'), + ('tx-parity-err', 'TX parity error bits'), + ('rx-stop', 'RX stop bits'), + ('tx-stop', 'TX stop bits'), + ('rx-warnings', 'RX warnings'), + ('tx-warnings', 'TX warnings'), + ('rx-data-bits', 'RX data bits'), + ('tx-data-bits', 'TX data bits'), ) - annotations = [ - ['rx-data', 'RX data'], - ['tx-data', 'TX data'], - ['rx-start', 'RX start bits'], - ['tx-start', 'TX start bits'], - ['rx-parity-ok', 'RX parity OK bits'], - ['tx-parity-ok', 'TX parity OK bits'], - ['rx-parity-err', 'RX parity error bits'], - ['tx-parity-err', 'TX parity error bits'], - ['rx-stop', 'RX stop bits'], - ['tx-stop', 'TX stop bits'], - ['rx-warnings', 'RX warnings'], - ['tx-warnings', 'TX warnings'], - ['rx-data-bits', 'RX data bits'], - ['tx-data-bits', 'TX data bits'], - ] annotation_rows = ( ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), @@ -173,7 +179,7 @@ class Decoder(srd.Decoder): def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: - self.samplerate = value; + self.samplerate = value # The width of one UART bit in number of samples. self.bit_width = float(self.samplerate) / float(self.options['baudrate']) @@ -240,12 +246,9 @@ class Decoder(srd.Decoder): self.databyte[rxtx] >>= 1 self.databyte[rxtx] |= \ (signal << (self.options['num_data_bits'] - 1)) - elif self.options['bit_order'] == 'msb-first': + else: self.databyte[rxtx] <<= 1 self.databyte[rxtx] |= (signal << 0) - else: - raise Exception('Invalid bit order value: %s', - self.options['bit_order']) self.putg([rxtx + 12, ['%d' % signal]]) @@ -275,8 +278,6 @@ class Decoder(srd.Decoder): self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) elif f == 'bin': self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) - else: - raise Exception('Invalid data format option: %s' % f) self.putbin(rxtx, (rxtx, bytes([b]))) self.putbin(rxtx, (2, bytes([b]))) @@ -328,8 +329,8 @@ class Decoder(srd.Decoder): self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') for (self.samplenum, pins) in data: # Note: Ignoring identical samples here for performance reasons @@ -338,10 +339,15 @@ class Decoder(srd.Decoder): # continue self.oldpins, (rx, tx) = pins, pins + if self.options['invert_rx'] == 'yes': + rx = not rx + if self.options['invert_tx'] == 'yes': + tx = not tx + # Either RX or TX (but not both) can be omitted. has_pin = [rx in (0, 1), tx in (0, 1)] if has_pin == [False, False]: - raise Exception('Either TX or RX (or both) pins required.') + raise ChannelError('Either TX or RX (or both) pins required.') # State machine. for rxtx in (RX, TX): @@ -361,9 +367,6 @@ class Decoder(srd.Decoder): self.get_parity_bit(rxtx, signal) elif self.state[rxtx] == 'GET STOP BITS': self.get_stop_bits(rxtx, signal) - else: - raise Exception('Invalid state: %s' % self.state[rxtx]) # Save current RX/TX values for the next round. self.oldbit[rxtx] = signal -