X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=b8508a72c74b7338e7a1039ce6e265e84badda2c;hb=95d11271b46a46788d497481d03177e883c8554e;hp=57031d73040643565cd6a6d5766bbc9058d3f0af;hpb=6a15597a7b3f901b566b7bfc8c484a14e0fb6a11;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 57031d7..b8508a7 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -23,10 +23,10 @@ import sigrokdecode as srd ''' OUTPUT_PYTHON format: -UART packet: -[, , ] +Packet: +[, , ] -This is the list of s and their respective : +This is the list of s and their respective values: - 'STARTBIT': The data is the (integer) value of the start bit (0/1). - 'DATA': The data is the (integer) value of the UART data. Valid values range from 0 to 512 (as the data can be up to 9 bits in size). @@ -66,11 +66,15 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits): return (ones % 2) == 1 elif parity_type == 'even': return (ones % 2) == 0 - else: - raise Exception('Invalid parity type: %d' % parity_type) + +class SamplerateError(Exception): + pass + +class ChannelError(Exception): + pass class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'uart' name = 'UART' longname = 'Universal Asynchronous Receiver/Transmitter' @@ -98,7 +102,10 @@ class Decoder(srd.Decoder): 'values': ('lsb-first', 'msb-first')}, {'id': 'format', 'desc': 'Data format', 'default': 'ascii', 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, - # TODO: Options to invert the signal(s). + {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no', + 'values': ('yes', 'no')}, + {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', + 'values': ('yes', 'no')}, ) annotations = ( ('rx-data', 'RX data'), @@ -172,7 +179,7 @@ class Decoder(srd.Decoder): def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: - self.samplerate = value; + self.samplerate = value # The width of one UART bit in number of samples. self.bit_width = float(self.samplerate) / float(self.options['baudrate']) @@ -239,12 +246,9 @@ class Decoder(srd.Decoder): self.databyte[rxtx] >>= 1 self.databyte[rxtx] |= \ (signal << (self.options['num_data_bits'] - 1)) - elif self.options['bit_order'] == 'msb-first': + else: self.databyte[rxtx] <<= 1 self.databyte[rxtx] |= (signal << 0) - else: - raise Exception('Invalid bit order value: %s', - self.options['bit_order']) self.putg([rxtx + 12, ['%d' % signal]]) @@ -274,8 +278,6 @@ class Decoder(srd.Decoder): self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) elif f == 'bin': self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) - else: - raise Exception('Invalid data format option: %s' % f) self.putbin(rxtx, (rxtx, bytes([b]))) self.putbin(rxtx, (2, bytes([b]))) @@ -327,8 +329,8 @@ class Decoder(srd.Decoder): self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) def decode(self, ss, es, data): - if self.samplerate is None: - raise Exception("Cannot decode without samplerate.") + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') for (self.samplenum, pins) in data: # Note: Ignoring identical samples here for performance reasons @@ -337,10 +339,15 @@ class Decoder(srd.Decoder): # continue self.oldpins, (rx, tx) = pins, pins + if self.options['invert_rx'] == 'yes': + rx = not rx + if self.options['invert_tx'] == 'yes': + tx = not tx + # Either RX or TX (but not both) can be omitted. has_pin = [rx in (0, 1), tx in (0, 1)] if has_pin == [False, False]: - raise Exception('Either TX or RX (or both) pins required.') + raise ChannelError('Either TX or RX (or both) pins required.') # State machine. for rxtx in (RX, TX): @@ -360,9 +367,6 @@ class Decoder(srd.Decoder): self.get_parity_bit(rxtx, signal) elif self.state[rxtx] == 'GET STOP BITS': self.get_stop_bits(rxtx, signal) - else: - raise Exception('Invalid state: %s' % self.state[rxtx]) # Save current RX/TX values for the next round. self.oldbit[rxtx] = signal -