X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=802c5937d93ccc223d6bfb74dfae822dfe7d6cb1;hb=9d09d6eddd838dc7720118a13772b980107c7399;hp=8db3e172dcc4f14ee56fff0fe1062d8188a2f275;hpb=dcd3d6262c57d86581864e642ec00dda5342d1af;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 8db3e17..802c593 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -18,6 +18,7 @@ ## import sigrokdecode as srd +from common.srdhelper import bitpack from math import floor, ceil ''' @@ -38,7 +39,11 @@ This is the list of s and their respective values: - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). - 'PARITY ERROR': The data is a tuple with two entries. The first one is the expected parity value, the second is the actual parity value. - - TODO: Frame error? + - 'BREAK': The data is always 0. + - 'FRAME': The data is always a tuple containing two items: The (integer) + value of the UART data, and a boolean which reflects the validity of the + UART frame. + - 'IDLE': The data is always 0. The field is 0 for RX packets, 1 for TX packets. ''' @@ -83,6 +88,7 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['uart'] + tags = ['Embedded/industrial'] optional_channels = ( # Allow specifying only one of the signals, e.g. if only one data # direction exists (or is relevant). @@ -107,6 +113,12 @@ class Decoder(srd.Decoder): 'values': ('yes', 'no')}, {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', 'values': ('yes', 'no')}, + {'id': 'rx_packet_delimiter', 'desc': 'RX packet delimiter (decimal)', + 'default': -1}, + {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)', + 'default': -1}, + {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1}, + {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1}, ) annotations = ( ('rx-data', 'RX data'), @@ -123,14 +135,22 @@ class Decoder(srd.Decoder): ('tx-warnings', 'TX warnings'), ('rx-data-bits', 'RX data bits'), ('tx-data-bits', 'TX data bits'), + ('rx-break', 'RX break'), + ('tx-break', 'TX break'), + ('rx-packet', 'RX packet'), + ('tx-packet', 'TX packet'), ) annotation_rows = ( - ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), + ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-warnings', 'RX warnings', (10,)), - ('tx-data', 'TX', (1, 3, 5, 7, 9)), + ('rx-break', 'RX break', (14,)), + ('rx-packets', 'RX packets', (16,)), ('tx-data-bits', 'TX bits', (13,)), + ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-warnings', 'TX warnings', (11,)), + ('tx-break', 'TX break', (15,)), + ('tx-packets', 'TX packets', (17,)), ) binary = ( ('rx', 'RX dump'), @@ -143,6 +163,10 @@ class Decoder(srd.Decoder): s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data) + def putx_packet(self, rxtx, data): + s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data) + def putpx(self, rxtx, data): s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data) @@ -155,14 +179,24 @@ class Decoder(srd.Decoder): s, halfbit = self.samplenum, self.bit_width / 2.0 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) + def putgse(self, ss, es, data): + self.put(ss, es, self.out_ann, data) + + def putpse(self, ss, es, data): + self.put(ss, es, self.out_python, data) + def putbin(self, rxtx, data): s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] + self.frame_valid = [None, None] self.startbit = [-1, -1] self.cur_data_bit = [0, 0] self.datavalue = [0, 0] @@ -171,6 +205,10 @@ class Decoder(srd.Decoder): self.startsample = [-1, -1] self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] self.databits = [[], []] + self.break_start = [None, None] + self.packet_cache = [[], []] + self.ss_packet, self.es_packet = [None, None], [None, None] + self.idle_start = [None, None] def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -185,7 +223,7 @@ class Decoder(srd.Decoder): self.bit_width = float(self.samplerate) / float(self.options['baudrate']) def get_sample_point(self, rxtx, bitnum): - """Determine absolute sample number of a bit slot's sample point.""" + # Determine absolute sample number of a bit slot's sample point. # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). @@ -195,30 +233,14 @@ class Decoder(srd.Decoder): bitpos += bitnum * self.bit_width return bitpos - # Return true if we reached the middle of the desired bit, false otherwise. - def reached_bit(self, rxtx, bitnum): - bitpos = self.get_sample_point(rxtx, bitnum) - if self.samplenum >= bitpos: - return True - return False - def wait_for_start_bit(self, rxtx, signal): - # The caller already has detected an edge. Strictly speaking this - # check on the current signal level is redundant. But it does not - # harm either. - if signal != 0: - return - # Save the sample number where the start bit begins. self.frame_start[rxtx] = self.samplenum + self.frame_valid[rxtx] = True self.state[rxtx] = 'GET START BIT' def get_start_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the start bit. - if not self.reached_bit(rxtx, 0): - return - self.startbit[rxtx] = signal # The startbit must be 0. If not, we report an error and wait @@ -226,6 +248,10 @@ class Decoder(srd.Decoder): if self.startbit[rxtx] != 0: self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) + self.frame_valid[rxtx] = False + es = self.samplenum + ceil(self.bit_width / 2.0) + self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx, + (self.datavalue[rxtx], self.frame_valid[rxtx])]) self.state[rxtx] = 'WAIT FOR START BIT' return @@ -233,29 +259,40 @@ class Decoder(srd.Decoder): self.datavalue[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = 'GET DATA BITS' - self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) - def get_data_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the desired data bit. - if not self.reached_bit(rxtx, 1 + self.cur_data_bit[rxtx]): + self.state[rxtx] = 'GET DATA BITS' + + def handle_packet(self, rxtx): + d = 'rx' if (rxtx == RX) else 'tx' + delim = self.options[d + '_packet_delimiter'] + plen = self.options[d + '_packet_len'] + if delim == -1 and plen == -1: return + # Cache data values until we see the delimiter and/or the specified + # packet length has been reached (whichever happens first). + if len(self.packet_cache[rxtx]) == 0: + self.ss_packet[rxtx] = self.startsample[rxtx] + self.packet_cache[rxtx].append(self.datavalue[rxtx]) + if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen: + self.es_packet[rxtx] = self.samplenum + s = '' + for b in self.packet_cache[rxtx]: + s += self.format_value(b) + if self.options['format'] != 'ascii': + s += ' ' + if self.options['format'] != 'ascii' and s[-1] == ' ': + s = s[:-1] # Drop trailing space. + self.putx_packet(rxtx, [16 + rxtx, [s]]) + self.packet_cache[rxtx] = [] + + def get_data_bits(self, rxtx, signal): # Save the sample number of the middle of the first data bit. if self.startsample[rxtx] == -1: self.startsample[rxtx] = self.samplenum - # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == 'lsb-first': - self.datavalue[rxtx] >>= 1 - self.datavalue[rxtx] |= \ - (signal << (self.options['num_data_bits'] - 1)) - else: - self.datavalue[rxtx] <<= 1 - self.datavalue[rxtx] |= (signal << 0) - self.putg([rxtx + 12, ['%d' % signal]]) # Store individual data bits and their start/end samplenumbers. @@ -267,12 +304,11 @@ class Decoder(srd.Decoder): if self.cur_data_bit[rxtx] < self.options['num_data_bits']: return - # Skip to either reception of the parity bit, or reception of - # the STOP bits if parity is not applicable. - self.state[rxtx] = 'GET PARITY BIT' - if self.options['parity_type'] == 'none': - self.state[rxtx] = 'GET STOP BITS' - + # Convert accumulated data bits to a data value. + bits = [b[0] for b in self.databits[rxtx]] + if self.options['bit_order'] == 'msb-first': + bits.reverse() + self.datavalue[rxtx] = bitpack(bits) self.putpx(rxtx, ['DATA', rxtx, (self.datavalue[rxtx], self.databits[rxtx])]) @@ -285,8 +321,16 @@ class Decoder(srd.Decoder): self.putbin(rxtx, [rxtx, bdata]) self.putbin(rxtx, [2, bdata]) + self.handle_packet(rxtx) + self.databits[rxtx] = [] + # Advance to either reception of the parity bit, or reception of + # the STOP bits if parity is not applicable. + self.state[rxtx] = 'GET PARITY BIT' + if self.options['parity_type'] == 'none': + self.state[rxtx] = 'GET STOP BITS' + def format_value(self, v): # Format value 'v' according to configured options. # Reflects the user selected kind of representation, as well as @@ -330,14 +374,8 @@ class Decoder(srd.Decoder): return None def get_parity_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the parity bit. - if not self.reached_bit(rxtx, 1 + self.options['num_data_bits']): - return - self.paritybit[rxtx] = signal - self.state[rxtx] = 'GET STOP BITS' - if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.datavalue[rxtx], self.options['num_data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) @@ -346,37 +384,42 @@ class Decoder(srd.Decoder): # TODO: Return expected/actual parity values. self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) + self.frame_valid[rxtx] = False + + self.state[rxtx] = 'GET STOP BITS' # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity_type'] == 'none' else 1 - b = 1 + self.options['num_data_bits'] + skip_parity - if not self.reached_bit(rxtx, b): - return - self.stopbit1[rxtx] = signal # Stop bits must be 1. If not, we report an error. if self.stopbit1[rxtx] != 1: self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) - # TODO: Abort? Ignore the frame? Other? - - self.state[rxtx] = 'WAIT FOR START BIT' + self.frame_valid[rxtx] = False self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) - def get_wait_cond(self, rxtx, inv): - """ - Determine Decoder.wait() condition for specified UART line. + # Pass the complete UART frame to upper layers. + es = self.samplenum + ceil(self.bit_width / 2.0) + self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx, + (self.datavalue[rxtx], self.frame_valid[rxtx])]) - Returns condititions that are suitable for Decoder.wait(). Those - conditions either match the falling edge of the START bit, or - the sample point of the next bit time. - """ + self.state[rxtx] = 'WAIT FOR START BIT' + self.idle_start[rxtx] = self.frame_start[rxtx] + self.frame_len_sample_count + + def handle_break(self, rxtx): + self.putpse(self.frame_start[rxtx], self.samplenum, + ['BREAK', rxtx, 0]) + self.putgse(self.frame_start[rxtx], self.samplenum, + [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']]) + self.state[rxtx] = 'WAIT FOR START BIT' + def get_wait_cond(self, rxtx, inv): + # Return condititions that are suitable for Decoder.wait(). Those + # conditions either match the falling edge of the START bit, or + # the sample point of the next bit time. state = self.state[rxtx] if state == 'WAIT FOR START BIT': return {rxtx: 'r' if inv else 'f'} @@ -389,11 +432,71 @@ class Decoder(srd.Decoder): elif state == 'GET STOP BITS': bitnum = 1 + self.options['num_data_bits'] bitnum += 0 if self.options['parity_type'] == 'none' else 1 - want_num = self.get_sample_point(rxtx, bitnum) - # want_num = int(want_num + 0.5) - want_num = ceil(want_num) - cond = {'skip': want_num - self.samplenum} - return cond + want_num = ceil(self.get_sample_point(rxtx, bitnum)) + return {'skip': want_num - self.samplenum} + + def get_idle_cond(self, rxtx, inv): + # Return a condition that corresponds to the (expected) end of + # the next frame, assuming that it will be an "idle frame" + # (constant high input level for the frame's length). + if self.idle_start[rxtx] is None: + return None + end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count + if end_of_frame < self.samplenum: + return None + return {'skip': end_of_frame - self.samplenum} + + def inspect_sample(self, rxtx, signal, inv): + # Inspect a sample returned by .wait() for the specified UART line. + if inv: + signal = not signal + + state = self.state[rxtx] + if state == 'WAIT FOR START BIT': + self.wait_for_start_bit(rxtx, signal) + elif state == 'GET START BIT': + self.get_start_bit(rxtx, signal) + elif state == 'GET DATA BITS': + self.get_data_bits(rxtx, signal) + elif state == 'GET PARITY BIT': + self.get_parity_bit(rxtx, signal) + elif state == 'GET STOP BITS': + self.get_stop_bits(rxtx, signal) + + def inspect_edge(self, rxtx, signal, inv): + # Inspect edges, independently from traffic, to detect break conditions. + if inv: + signal = not signal + if not signal: + # Signal went low. Start another interval. + self.break_start[rxtx] = self.samplenum + return + # Signal went high. Was there an extended period with low signal? + if self.break_start[rxtx] is None: + return + diff = self.samplenum - self.break_start[rxtx] + if diff >= self.break_min_sample_count: + self.handle_break(rxtx) + self.break_start[rxtx] = None + + def inspect_idle(self, rxtx, signal, inv): + # Check each edge and each period of stable input (either level). + # Can derive the "idle frame period has passed" condition. + if inv: + signal = not signal + if not signal: + # Low input, cease inspection. + self.idle_start[rxtx] = None + return + # High input, either just reached, or still stable. + if self.idle_start[rxtx] is None: + self.idle_start[rxtx] = self.samplenum + diff = self.samplenum - self.idle_start[rxtx] + if diff < self.frame_len_sample_count: + return + ss, es = self.idle_start[rxtx], self.samplenum + self.putpse(ss, es, ['IDLE', rxtx, 0]) + self.idle_start[rxtx] = self.samplenum def decode(self): if not self.samplerate: @@ -405,34 +508,54 @@ class Decoder(srd.Decoder): opt = self.options inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] + cond_data_idx = [None] * len(has_pin) + + # Determine the number of samples for a complete frame's time span. + # A period of low signal (at least) that long is a break condition. + frame_samples = 1 # START + frame_samples += self.options['num_data_bits'] + frame_samples += 0 if self.options['parity_type'] == 'none' else 1 + frame_samples += self.options['num_stop_bits'] + frame_samples *= self.bit_width + self.frame_len_sample_count = ceil(frame_samples) + self.break_min_sample_count = self.frame_len_sample_count + cond_edge_idx = [None] * len(has_pin) + cond_idle_idx = [None] * len(has_pin) while True: conds = [] if has_pin[RX]: + cond_data_idx[RX] = len(conds) conds.append(self.get_wait_cond(RX, inv[RX])) + cond_edge_idx[RX] = len(conds) + conds.append({RX: 'e'}) + cond_idle_idx[RX] = None + idle_cond = self.get_idle_cond(RX, inv[RX]) + if idle_cond: + cond_idle_idx[RX] = len(conds) + conds.append(idle_cond) if has_pin[TX]: + cond_data_idx[TX] = len(conds) conds.append(self.get_wait_cond(TX, inv[TX])) + cond_edge_idx[TX] = len(conds) + conds.append({TX: 'e'}) + cond_idle_idx[TX] = None + idle_cond = self.get_idle_cond(TX, inv[TX]) + if idle_cond: + cond_idle_idx[TX] = len(conds) + conds.append(idle_cond) (rx, tx) = self.wait(conds) - if inv[RX]: - rx = not rx - if inv[TX]: - tx = not tx - - # State machine. - for rxtx in (RX, TX): - # Don't try to handle RX (or TX) if not supplied. - if not has_pin[rxtx]: - continue - - signal = rx if (rxtx == RX) else tx - - if self.state[rxtx] == 'WAIT FOR START BIT': - self.wait_for_start_bit(rxtx, signal) - elif self.state[rxtx] == 'GET START BIT': - self.get_start_bit(rxtx, signal) - elif self.state[rxtx] == 'GET DATA BITS': - self.get_data_bits(rxtx, signal) - elif self.state[rxtx] == 'GET PARITY BIT': - self.get_parity_bit(rxtx, signal) - elif self.state[rxtx] == 'GET STOP BITS': - self.get_stop_bits(rxtx, signal) + if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]: + self.inspect_sample(RX, rx, inv[RX]) + if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]: + self.inspect_edge(RX, rx, inv[RX]) + self.inspect_idle(RX, rx, inv[RX]) + if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]: + self.inspect_idle(RX, rx, inv[RX]) + if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]: + self.inspect_sample(TX, tx, inv[TX]) + if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]: + self.inspect_edge(TX, tx, inv[TX]) + self.inspect_idle(TX, tx, inv[TX]) + if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]: + self.inspect_idle(TX, tx, inv[TX])