X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=802c5937d93ccc223d6bfb74dfae822dfe7d6cb1;hb=9d09d6eddd838dc7720118a13772b980107c7399;hp=0a0d30729c6bcf85de4b2edd0040e251b5dc05cf;hpb=ab0522b8722c883275c2d695471b0746ab7372a0;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 0a0d307..802c593 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -43,6 +43,7 @@ This is the list of s and their respective values: - 'FRAME': The data is always a tuple containing two items: The (integer) value of the UART data, and a boolean which reflects the validity of the UART frame. + - 'IDLE': The data is always 0. The field is 0 for RX packets, 1 for TX packets. ''' @@ -116,6 +117,8 @@ class Decoder(srd.Decoder): 'default': -1}, {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)', 'default': -1}, + {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1}, + {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1}, ) annotations = ( ('rx-data', 'RX data'), @@ -138,13 +141,13 @@ class Decoder(srd.Decoder): ('tx-packet', 'TX packet'), ) annotation_rows = ( - ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), + ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-warnings', 'RX warnings', (10,)), ('rx-break', 'RX break', (14,)), ('rx-packets', 'RX packets', (16,)), - ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-data-bits', 'TX bits', (13,)), + ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-warnings', 'TX warnings', (11,)), ('tx-break', 'TX break', (15,)), ('tx-packets', 'TX packets', (17,)), @@ -205,6 +208,7 @@ class Decoder(srd.Decoder): self.break_start = [None, None] self.packet_cache = [[], []] self.ss_packet, self.es_packet = [None, None], [None, None] + self.idle_start = [None, None] def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -261,16 +265,18 @@ class Decoder(srd.Decoder): self.state[rxtx] = 'GET DATA BITS' def handle_packet(self, rxtx): - opt = ('rx' if (rxtx == RX) else 'tx') + '_packet_delimiter' - delim = self.options[opt] - if delim == -1: + d = 'rx' if (rxtx == RX) else 'tx' + delim = self.options[d + '_packet_delimiter'] + plen = self.options[d + '_packet_len'] + if delim == -1 and plen == -1: return - # Cache data values until we see the delimiter. + # Cache data values until we see the delimiter and/or the specified + # packet length has been reached (whichever happens first). if len(self.packet_cache[rxtx]) == 0: self.ss_packet[rxtx] = self.startsample[rxtx] self.packet_cache[rxtx].append(self.datavalue[rxtx]) - if self.datavalue[rxtx] == delim: + if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen: self.es_packet[rxtx] = self.samplenum s = '' for b in self.packet_cache[rxtx]: @@ -401,6 +407,7 @@ class Decoder(srd.Decoder): (self.datavalue[rxtx], self.frame_valid[rxtx])]) self.state[rxtx] = 'WAIT FOR START BIT' + self.idle_start[rxtx] = self.frame_start[rxtx] + self.frame_len_sample_count def handle_break(self, rxtx): self.putpse(self.frame_start[rxtx], self.samplenum, @@ -428,6 +435,17 @@ class Decoder(srd.Decoder): want_num = ceil(self.get_sample_point(rxtx, bitnum)) return {'skip': want_num - self.samplenum} + def get_idle_cond(self, rxtx, inv): + # Return a condition that corresponds to the (expected) end of + # the next frame, assuming that it will be an "idle frame" + # (constant high input level for the frame's length). + if self.idle_start[rxtx] is None: + return None + end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count + if end_of_frame < self.samplenum: + return None + return {'skip': end_of_frame - self.samplenum} + def inspect_sample(self, rxtx, signal, inv): # Inspect a sample returned by .wait() for the specified UART line. if inv: @@ -461,6 +479,25 @@ class Decoder(srd.Decoder): self.handle_break(rxtx) self.break_start[rxtx] = None + def inspect_idle(self, rxtx, signal, inv): + # Check each edge and each period of stable input (either level). + # Can derive the "idle frame period has passed" condition. + if inv: + signal = not signal + if not signal: + # Low input, cease inspection. + self.idle_start[rxtx] = None + return + # High input, either just reached, or still stable. + if self.idle_start[rxtx] is None: + self.idle_start[rxtx] = self.samplenum + diff = self.samplenum - self.idle_start[rxtx] + if diff < self.frame_len_sample_count: + return + ss, es = self.idle_start[rxtx], self.samplenum + self.putpse(ss, es, ['IDLE', rxtx, 0]) + self.idle_start[rxtx] = self.samplenum + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') @@ -480,8 +517,10 @@ class Decoder(srd.Decoder): frame_samples += 0 if self.options['parity_type'] == 'none' else 1 frame_samples += self.options['num_stop_bits'] frame_samples *= self.bit_width - self.break_min_sample_count = ceil(frame_samples) + self.frame_len_sample_count = ceil(frame_samples) + self.break_min_sample_count = self.frame_len_sample_count cond_edge_idx = [None] * len(has_pin) + cond_idle_idx = [None] * len(has_pin) while True: conds = [] @@ -490,17 +529,33 @@ class Decoder(srd.Decoder): conds.append(self.get_wait_cond(RX, inv[RX])) cond_edge_idx[RX] = len(conds) conds.append({RX: 'e'}) + cond_idle_idx[RX] = None + idle_cond = self.get_idle_cond(RX, inv[RX]) + if idle_cond: + cond_idle_idx[RX] = len(conds) + conds.append(idle_cond) if has_pin[TX]: cond_data_idx[TX] = len(conds) conds.append(self.get_wait_cond(TX, inv[TX])) cond_edge_idx[TX] = len(conds) conds.append({TX: 'e'}) + cond_idle_idx[TX] = None + idle_cond = self.get_idle_cond(TX, inv[TX]) + if idle_cond: + cond_idle_idx[TX] = len(conds) + conds.append(idle_cond) (rx, tx) = self.wait(conds) if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]: self.inspect_sample(RX, rx, inv[RX]) if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]: self.inspect_edge(RX, rx, inv[RX]) + self.inspect_idle(RX, rx, inv[RX]) + if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]: + self.inspect_idle(RX, rx, inv[RX]) if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]: self.inspect_sample(TX, tx, inv[TX]) if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]: self.inspect_edge(TX, tx, inv[TX]) + self.inspect_idle(TX, tx, inv[TX]) + if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]: + self.inspect_idle(TX, tx, inv[TX])