X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=6c3d85cf9b06c9f30db1d59c33aeab85b9ecb631;hb=ef7b15889de43ddd9d46aa53c86e29ee6e5999a8;hp=2c0a7da5a81446e129adb8f3803daeddb6db3871;hpb=0de2810f223fefc9e3040adaa7f1b97616c6931d;p=libsigrokdecode.git diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 2c0a7da..6c3d85c 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -18,6 +18,7 @@ ## import sigrokdecode as srd +from common.srdhelper import bitpack from math import floor, ceil ''' @@ -160,6 +161,9 @@ class Decoder(srd.Decoder): self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] @@ -185,7 +189,7 @@ class Decoder(srd.Decoder): self.bit_width = float(self.samplerate) / float(self.options['baudrate']) def get_sample_point(self, rxtx, bitnum): - """Determine absolute sample number of a bit slot's sample point.""" + # Determine absolute sample number of a bit slot's sample point. # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). @@ -195,30 +199,13 @@ class Decoder(srd.Decoder): bitpos += bitnum * self.bit_width return bitpos - # Return true if we reached the middle of the desired bit, false otherwise. - def reached_bit(self, rxtx, bitnum): - bitpos = self.get_sample_point(rxtx, bitnum) - if self.samplenum >= bitpos: - return True - return False - def wait_for_start_bit(self, rxtx, signal): - # The caller already has detected an edge. Strictly speaking this - # check on the current signal level is redundant. But it does not - # harm either. - if signal != 0: - return - # Save the sample number where the start bit begins. self.frame_start[rxtx] = self.samplenum self.state[rxtx] = 'GET START BIT' def get_start_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the start bit. - if not self.reached_bit(rxtx, 0): - return - self.startbit[rxtx] = signal # The startbit must be 0. If not, we report an error and wait @@ -233,29 +220,16 @@ class Decoder(srd.Decoder): self.datavalue[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = 'GET DATA BITS' - self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) - def get_data_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the desired data bit. - if not self.reached_bit(rxtx, 1 + self.cur_data_bit[rxtx]): - return + self.state[rxtx] = 'GET DATA BITS' + def get_data_bits(self, rxtx, signal): # Save the sample number of the middle of the first data bit. if self.startsample[rxtx] == -1: self.startsample[rxtx] = self.samplenum - # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == 'lsb-first': - self.datavalue[rxtx] >>= 1 - self.datavalue[rxtx] |= \ - (signal << (self.options['num_data_bits'] - 1)) - else: - self.datavalue[rxtx] <<= 1 - self.datavalue[rxtx] |= (signal << 0) - self.putg([rxtx + 12, ['%d' % signal]]) # Store individual data bits and their start/end samplenumbers. @@ -267,12 +241,11 @@ class Decoder(srd.Decoder): if self.cur_data_bit[rxtx] < self.options['num_data_bits']: return - # Skip to either reception of the parity bit, or reception of - # the STOP bits if parity is not applicable. - self.state[rxtx] = 'GET PARITY BIT' - if self.options['parity_type'] == 'none': - self.state[rxtx] = 'GET STOP BITS' - + # Convert accumulated data bits to a data value. + bits = [b[0] for b in self.databits[rxtx]] + if self.options['bit_order'] == 'msb-first': + bits.reverse() + self.datavalue[rxtx] = bitpack(bits) self.putpx(rxtx, ['DATA', rxtx, (self.datavalue[rxtx], self.databits[rxtx])]) @@ -287,6 +260,12 @@ class Decoder(srd.Decoder): self.databits[rxtx] = [] + # Advance to either reception of the parity bit, or reception of + # the STOP bits if parity is not applicable. + self.state[rxtx] = 'GET PARITY BIT' + if self.options['parity_type'] == 'none': + self.state[rxtx] = 'GET STOP BITS' + def format_value(self, v): # Format value 'v' according to configured options. # Reflects the user selected kind of representation, as well as @@ -330,14 +309,8 @@ class Decoder(srd.Decoder): return None def get_parity_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the parity bit. - if not self.reached_bit(rxtx, 1 + self.options['num_data_bits']): - return - self.paritybit[rxtx] = signal - self.state[rxtx] = 'GET STOP BITS' - if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.datavalue[rxtx], self.options['num_data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) @@ -347,14 +320,10 @@ class Decoder(srd.Decoder): self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) + self.state[rxtx] = 'GET STOP BITS' + # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity_type'] == 'none' else 1 - b = 1 + self.options['num_data_bits'] + skip_parity - if not self.reached_bit(rxtx, b): - return - self.stopbit1[rxtx] = signal # Stop bits must be 1. If not, we report an error. @@ -363,20 +332,15 @@ class Decoder(srd.Decoder): self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) # TODO: Abort? Ignore the frame? Other? - self.state[rxtx] = 'WAIT FOR START BIT' - self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) - def get_wait_cond(self, rxtx, inv): - """ - Determine Decoder.wait() condition for specified UART line. - - Returns condititions that are suitable for Decoder.wait(). Those - conditions either match the falling edge of the START bit, or - the sample point of the next bit time. - """ + self.state[rxtx] = 'WAIT FOR START BIT' + def get_wait_cond(self, rxtx, inv): + # Return condititions that are suitable for Decoder.wait(). Those + # conditions either match the falling edge of the START bit, or + # the sample point of the next bit time. state = self.state[rxtx] if state == 'WAIT FOR START BIT': return {rxtx: 'r' if inv else 'f'} @@ -389,15 +353,11 @@ class Decoder(srd.Decoder): elif state == 'GET STOP BITS': bitnum = 1 + self.options['num_data_bits'] bitnum += 0 if self.options['parity_type'] == 'none' else 1 - want_num = self.get_sample_point(rxtx, bitnum) - # want_num = int(want_num + 0.5) - want_num = ceil(want_num) - cond = {'skip': want_num - self.samplenum} - return cond + want_num = ceil(self.get_sample_point(rxtx, bitnum)) + return {'skip': want_num - self.samplenum} def inspect_sample(self, rxtx, signal, inv): - """Inspect a sample returned by .wait() for the specified UART line.""" - + # Inspect a sample returned by .wait() for the specified UART line. if inv: signal = not signal @@ -423,15 +383,18 @@ class Decoder(srd.Decoder): opt = self.options inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] + cond_idx = [None] * len(has_pin) while True: conds = [] if has_pin[RX]: + cond_idx[RX] = len(conds) conds.append(self.get_wait_cond(RX, inv[RX])) if has_pin[TX]: + cond_idx[TX] = len(conds) conds.append(self.get_wait_cond(TX, inv[TX])) (rx, tx) = self.wait(conds) - if has_pin[RX]: + if cond_idx[RX] is not None and self.matched[cond_idx[RX]]: self.inspect_sample(RX, rx, inv[RX]) - if has_pin[TX]: + if cond_idx[TX] is not None and self.matched[cond_idx[TX]]: self.inspect_sample(TX, tx, inv[TX])