X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=6c3d85cf9b06c9f30db1d59c33aeab85b9ecb631;hb=d0d63deadf5b841199c42721bc498fc5c9a86126;hp=152b8538e0f187e362e2317972b2d23ccf46bcc8;hpb=4bb42a91968b5b610c0c843024aa158e2f414805;p=libsigrokdecode.git

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 152b853..6c3d85c 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -18,6 +18,7 @@
 ##
 
 import sigrokdecode as srd
+from common.srdhelper import bitpack
 from math import floor, ceil
 
 '''
@@ -160,6 +161,9 @@ class Decoder(srd.Decoder):
         self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.samplenum = 0
         self.frame_start = [-1, -1]
@@ -185,7 +189,7 @@ class Decoder(srd.Decoder):
             self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
 
     def get_sample_point(self, rxtx, bitnum):
-        """Determine absolute sample number of a bit slot's sample point."""
+        # Determine absolute sample number of a bit slot's sample point.
         # bitpos is the samplenumber which is in the middle of the
         # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
         # (if used) or the first stop bit, and so on).
@@ -226,15 +230,6 @@ class Decoder(srd.Decoder):
         if self.startsample[rxtx] == -1:
             self.startsample[rxtx] = self.samplenum
 
-        # Get the next data bit in LSB-first or MSB-first fashion.
-        if self.options['bit_order'] == 'lsb-first':
-            self.datavalue[rxtx] >>= 1
-            self.datavalue[rxtx] |= \
-                (signal << (self.options['num_data_bits'] - 1))
-        else:
-            self.datavalue[rxtx] <<= 1
-            self.datavalue[rxtx] |= (signal << 0)
-
         self.putg([rxtx + 12, ['%d' % signal]])
 
         # Store individual data bits and their start/end samplenumbers.
@@ -246,6 +241,11 @@ class Decoder(srd.Decoder):
         if self.cur_data_bit[rxtx] < self.options['num_data_bits']:
             return
 
+        # Convert accumulated data bits to a data value.
+        bits = [b[0] for b in self.databits[rxtx]]
+        if self.options['bit_order'] == 'msb-first':
+            bits.reverse()
+        self.datavalue[rxtx] = bitpack(bits)
         self.putpx(rxtx, ['DATA', rxtx,
             (self.datavalue[rxtx], self.databits[rxtx])])
 
@@ -338,14 +338,9 @@ class Decoder(srd.Decoder):
         self.state[rxtx] = 'WAIT FOR START BIT'
 
     def get_wait_cond(self, rxtx, inv):
-        """
-        Determine Decoder.wait() condition for specified UART line.
-
-        Returns condititions that are suitable for Decoder.wait(). Those
-        conditions either match the falling edge of the START bit, or
-        the sample point of the next bit time.
-        """
-
+        # Return condititions that are suitable for Decoder.wait(). Those
+        # conditions either match the falling edge of the START bit, or
+        # the sample point of the next bit time.
         state = self.state[rxtx]
         if state == 'WAIT FOR START BIT':
             return {rxtx: 'r' if inv else 'f'}
@@ -358,15 +353,11 @@ class Decoder(srd.Decoder):
         elif state == 'GET STOP BITS':
             bitnum = 1 + self.options['num_data_bits']
             bitnum += 0 if self.options['parity_type'] == 'none' else 1
-        want_num = self.get_sample_point(rxtx, bitnum)
-        # want_num = int(want_num + 0.5)
-        want_num = ceil(want_num)
-        cond = {'skip': want_num - self.samplenum}
-        return cond
+        want_num = ceil(self.get_sample_point(rxtx, bitnum))
+        return {'skip': want_num - self.samplenum}
 
     def inspect_sample(self, rxtx, signal, inv):
-        """Inspect a sample returned by .wait() for the specified UART line."""
-
+        # Inspect a sample returned by .wait() for the specified UART line.
         if inv:
             signal = not signal