X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Ftca6408a%2Fpd.py;h=4ca1082a8bcfe9e2645d46ac502063332d898530;hb=HEAD;hp=01c4e6d9bc764acd5db50458b1058d4b3b6236f3;hpb=9b6c0354ce4bab15c524928f2c0059f1df543ad9;p=libsigrokdecode.git diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py index 01c4e6d..4ca1082 100644 --- a/decoders/tca6408a/pd.py +++ b/decoders/tca6408a/pd.py @@ -57,33 +57,33 @@ class Decoder(srd.Decoder): self.state = 'IDLE' self.chip = -1 - self.logic_es = 1 - self.logic_data = [] - for i in range(NUM_OUTPUT_CHANNELS): - self.logic_data.append(bytes([1])) + self.logic_output_es = 0 + self.logic_value = 0 def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) self.out_logic = self.register(srd.OUTPUT_LOGIC) + def flush(self): + self.put_logic_states() + def putx(self, data): self.put(self.ss, self.es, self.out_ann, data) def put_logic_states(self): - if (self.es > self.logic_es): - for i in range(NUM_OUTPUT_CHANNELS): - self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]]) - self.logic_es = self.es + if (self.es > self.logic_output_es): + data = bytes([self.logic_value]) + self.put(self.logic_output_es, self.es, self.out_logic, [0, data]) + self.logic_output_es = self.es def handle_reg_0x00(self, b): self.putx([1, ['State of inputs: %02X' % b]]) # TODO def handle_reg_0x01(self, b): + self.put_logic_states() self.putx([1, ['Outputs set: %02X' % b]]) - for i in range(NUM_OUTPUT_CHANNELS): - bit = (b & (1 << i)) != 0 - self.logic_data[i] = bytes([bit]) + self.logic_value = b def handle_reg_0x02(self, b): self.putx([1, ['Polarity inverted: %02X' % b]]) @@ -113,8 +113,6 @@ class Decoder(srd.Decoder): # Store the start/end samples of this I²C packet. self.ss, self.es = ss, es - self.put_logic_states() - # State machine. if self.state == 'IDLE': # Wait for an I²C START condition.