X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Ftca6408a%2Fpd.py;h=01c4e6d9bc764acd5db50458b1058d4b3b6236f3;hb=9b6c0354ce4bab15c524928f2c0059f1df543ad9;hp=1f90245c8f725093b757121d2b19cabb466afc69;hpb=486b19ce017c6663be6574dacd0c823304903bca;p=libsigrokdecode.git

diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py
index 1f90245..01c4e6d 100644
--- a/decoders/tca6408a/pd.py
+++ b/decoders/tca6408a/pd.py
@@ -16,46 +16,74 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
 
+NUM_OUTPUT_CHANNELS = 8
+
+def logic_channels(num_channels):
+    l = []
+    for i in range(num_channels):
+        l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
+    return tuple(l)
+
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'tca6408a'
     name = 'TI TCA6408A'
     longname = 'Texas Instruments TCA6408A'
     desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['tca6408a']
+    outputs = []
+    tags = ['Embedded/industrial', 'IC']
     annotations = (
         ('register', 'Register type'),
         ('value', 'Register value'),
-        ('warnings', 'Warning messages'),
+        ('warning', 'Warning'),
     )
+    logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
     annotation_rows = (
         ('regs', 'Registers', (0, 1)),
         ('warnings', 'Warnings', (2,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'IDLE'
         self.chip = -1
 
+        self.logic_es = 1
+        self.logic_data = []
+        for i in range(NUM_OUTPUT_CHANNELS):
+            self.logic_data.append(bytes([1]))
+
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_logic = self.register(srd.OUTPUT_LOGIC)
 
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
+    def put_logic_states(self):
+        if (self.es > self.logic_es):
+            for i in range(NUM_OUTPUT_CHANNELS):
+                self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
+            self.logic_es = self.es
+
     def handle_reg_0x00(self, b):
         self.putx([1, ['State of inputs: %02X' % b]])
+        # TODO
 
     def handle_reg_0x01(self, b):
-        self.putx([1, ['Outputs set: %02X' % b ]])
+        self.putx([1, ['Outputs set: %02X' % b]])
+        for i in range(NUM_OUTPUT_CHANNELS):
+            bit = (b & (1 << i)) != 0
+            self.logic_data[i] = bytes([bit])
 
     def handle_reg_0x02(self, b):
         self.putx([1, ['Polarity inverted: %02X' % b]])
@@ -85,6 +113,8 @@ class Decoder(srd.Decoder):
         # Store the start/end samples of this I²C packet.
         self.ss, self.es = ss, es
 
+        self.put_logic_states()
+
         # State machine.
         if self.state == 'IDLE':
             # Wait for an I²C START condition.
@@ -92,7 +122,7 @@ class Decoder(srd.Decoder):
                 return
             self.state = 'GET SLAVE ADDR'
         elif self.state == 'GET SLAVE ADDR':
-            self.chip = databyte  
+            self.chip = databyte
             self.state = 'GET REG ADDR'
         elif self.state == 'GET REG ADDR':
             # Wait for a data write (master selects the slave register).