X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspiflash%2Fpd.py;h=aecc2d37db5766ce8e994177f05b3b9396f15df9;hb=546733a262c826ee5bc9ee74eaec330d2e3c088b;hp=304545f92ba8dcd871fe01edeffa9e81dcd5ca74;hpb=539e6dafe7889e76061b9015ac522699d46082c0;p=libsigrokdecode.git

diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py
index 304545f..aecc2d3 100644
--- a/decoders/spiflash/pd.py
+++ b/decoders/spiflash/pd.py
@@ -217,6 +217,8 @@ class Decoder(srd.Decoder):
             self.putx([Ann.BIT, [decode_status_reg(miso)]])
             self.putx([Ann.FIELD, ['Status register']])
             self.putc([Ann.RDSR, self.cmd_ann_list()])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         self.cmdstate += 1
 
     def handle_rdsr2(self, mosi, miso):
@@ -246,12 +248,14 @@ class Decoder(srd.Decoder):
             self.emit_cmd_byte()
         elif self.cmdstate == 2:
             # Byte 2: Master sends status register 1.
-            self.putx([Ann.BIT, [decode_status_reg(miso)]])
+            self.putx([Ann.BIT, [decode_status_reg(mosi)]])
             self.putx([Ann.FIELD, ['Status register 1']])
+            # Set write latch state.
+            self.writestate = 1 if (miso & (1 << 1)) else 0
         elif self.cmdstate == 3:
             # Byte 3: Master sends status register 2.
             # TODO: Decode status register 2 correctly.
-            self.putx([Ann.BIT, [decode_status_reg(miso)]])
+            self.putx([Ann.BIT, [decode_status_reg(mosi)]])
             self.putx([Ann.FIELD, ['Status register 2']])
             self.es_cmd = self.es
             self.putc([Ann.WRSR, self.cmd_ann_list()])