X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspiflash%2Fpd.py;h=26f3a24c3105f67c67d44ee40d42dbaf926e34b1;hb=07da8a9b7b4c6e433b2246e65c712f4b2dbcc856;hp=536b55c56521f7e8bda7786115150d365810a988;hpb=51a91ed0e544e1e5c214040b714b5263846700c0;p=libsigrokdecode.git diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py index 536b55c..26f3a24 100644 --- a/decoders/spiflash/pd.py +++ b/decoders/spiflash/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2011-2016 Uwe Hermann +## Copyright (C) 2011-2020 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,16 +18,14 @@ ## import sigrokdecode as srd +import re +from common.srdhelper import SrdIntEnum from .lists import * L = len(cmds) -# Don't forget to keep this in sync with 'cmds' is lists.py. -class Ann: - WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \ - RDSR2, CE, ESRY, DSRY, WRITE1, WRITE2, REMS, RDID, RDP_RES, CP, ENSO, DP, \ - READ2X, EXSO, CE2, STATUS, BE, REMS2, \ - BIT, FIELD, WARN = range(L + 3) +a = [re.sub('\/', '_', c[0]).replace('2READ', 'READ2X') for c in cmds.values()] + ['BIT', 'FIELD', 'WARN'] +Ann = SrdIntEnum.from_list('Ann', a) def cmd_annotation_classes(): return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()]) @@ -73,12 +71,13 @@ def decode_status_reg(data): class Decoder(srd.Decoder): api_version = 3 id = 'spiflash' - name = 'SPI flash' - longname = 'SPI flash chips' - desc = 'xx25 series SPI (NOR) flash chip protocol.' + name = 'SPI flash/EEPROM' + longname = 'SPI flash/EEPROM chips' + desc = 'xx25 series SPI (NOR) flash/EEPROM chip protocol.' license = 'gplv2+' inputs = ['spi'] - outputs = ['spiflash'] + outputs = [] + tags = ['IC', 'Memory'] annotations = cmd_annotation_classes() + ( ('bit', 'Bit'), ('field', 'Field'), @@ -104,6 +103,7 @@ class Decoder(srd.Decoder): self.device_id = -1 self.on_end_transaction = None self.end_current_transaction() + self.writestate = 0 # Build dict mapping command keys to handler functions. Each # command in 'cmds' (defined in lists.py) has a matching @@ -174,10 +174,11 @@ class Decoder(srd.Decoder): def handle_wren(self, mosi, miso): self.putx([Ann.WREN, self.cmd_ann_list()]) - self.state = None + self.writestate = 1 def handle_wrdi(self, mosi, miso): - pass # TODO + self.putx([Ann.WRDI, self.cmd_ann_list()]) + self.writestate = 0 def handle_rdid(self, mosi, miso): if self.cmdstate == 1: @@ -215,6 +216,8 @@ class Decoder(srd.Decoder): self.putx([Ann.BIT, [decode_status_reg(miso)]]) self.putx([Ann.FIELD, ['Status register']]) self.putc([Ann.RDSR, self.cmd_ann_list()]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 self.cmdstate += 1 def handle_rdsr2(self, mosi, miso): @@ -244,12 +247,14 @@ class Decoder(srd.Decoder): self.emit_cmd_byte() elif self.cmdstate == 2: # Byte 2: Master sends status register 1. - self.putx([Ann.BIT, [decode_status_reg(miso)]]) + self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 1']]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 elif self.cmdstate == 3: # Byte 3: Master sends status register 2. # TODO: Decode status register 2 correctly. - self.putx([Ann.BIT, [decode_status_reg(miso)]]) + self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 2']]) self.es_cmd = self.es self.putc([Ann.WRSR, self.cmd_ann_list()]) @@ -279,6 +284,8 @@ class Decoder(srd.Decoder): if self.cmdstate == 1: # Byte 1: Master sends command ID. self.emit_cmd_byte() + if self.writestate == 0: + self.putc([Ann.WARN, ['Warning: WREN might be missing']]) elif self.cmdstate in (2, 3, 4): # Bytes 2/3/4: Master sends write address (24bits, MSB-first). self.emit_addr_bytes(mosi) @@ -363,11 +370,12 @@ class Decoder(srd.Decoder): self.cmdstate += 1 # TODO: Warn/abort if we don't see the necessary amount of bytes. - # TODO: Warn if WREN was not seen before. def handle_se(self, mosi, miso): if self.cmdstate == 1: # Byte 1: Master sends command ID. self.emit_cmd_byte() + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) elif self.cmdstate in (2, 3, 4): # Bytes 2/3/4: Master sends sector address (24bits, MSB-first). self.emit_addr_bytes(mosi) @@ -387,13 +395,15 @@ class Decoder(srd.Decoder): def handle_be(self, mosi, miso): pass # TODO - # TODO: Warn if WREN was not seen before. def handle_ce(self, mosi, miso): self.putx([Ann.CE, self.cmd_ann_list()]) + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) - # TODO: Warn if WREN was not seen before. def handle_ce2(self, mosi, miso): self.putx([Ann.CE2, self.cmd_ann_list()]) + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) def handle_pp(self, mosi, miso): # Page program: Master asserts CS#, sends PP command, sends 3-byte @@ -462,8 +472,8 @@ class Decoder(srd.Decoder): self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) if self.cmdstate == 6: - id = self.ids[1] if self.manufacturer_id_first else self.ids[0] - self.device_id = id + id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0] + self.device_id = id_ self.es_cmd = self.es self.putc([Ann.REMS, self.cmd_vendor_dev_list()]) self.state = None