X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi.py;h=457abb5bde2f962cdd2c325023944eb6e9017aa9;hb=0db89774dee57db500f270985f73f3bb2dcdbb42;hp=44d07c260f64bf19d057dc2fac42533d42e91d2d;hpb=d6bace96eda41684bdd4136a009bb261d36e8fd2;p=libsigrokdecode.git diff --git a/decoders/spi.py b/decoders/spi.py index 44d07c2..457abb5 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -21,6 +21,22 @@ import sigrokdecode as srd +# Chip-select options +ACTIVE_LOW = 0 +ACTIVE_HIGH = 1 + +# Clock polarity options +CPOL_0 = 0 # Clock is low when inactive +CPOL_1 = 1 # Clock is high when inactive + +# Clock phase options +CPHA_0 = 0 # Data is valid on the rising clock edge +CPHA_1 = 1 # Data is valid on the falling clock edge + +# Bit order options +MSB_FIRST = 0 +LSB_FIRST = 1 + # Annotation formats ANN_HEX = 0 @@ -43,7 +59,13 @@ class Decoder(srd.Decoder): {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, ] - options = {} + options = { + 'cs_active_low': ['CS# active low', ACTIVE_LOW], + 'clock_polarity': ['Clock polarity', CPOL_0], + 'clock_phase': ['Clock phase', CPHA_0], + 'bit_order': ['Bit order within the SPI data', MSB_FIRST], + 'word_size': ['Word size of SPI data', 8], # 1-64? + } annotations = [ ['Hex', 'SPI data bytes in hex format'], ] @@ -56,6 +78,13 @@ class Decoder(srd.Decoder): self.bytesreceived = 0 self.samplenum = -1 + # Set protocol decoder option defaults. + self.cs_active_low = Decoder.options['cs_active_low'][1] + self.clock_polarity = Decoder.options['clock_polarity'][1] + self.clock_phase = Decoder.options['clock_phase'][1] + self.bit_order = Decoder.options['bit_order'][1] + self.word_size = Decoder.options['word_size'][1] + def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')