X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi.py;h=44d07c260f64bf19d057dc2fac42533d42e91d2d;hb=9b4d8a5753db586648abfe7897c29ad5d5bc77a5;hp=997119cad8e9e55573706cc199938a7455b7777e;hpb=6eb875784c96db52e962f40df24035c31c5be738;p=libsigrokdecode.git diff --git a/decoders/spi.py b/decoders/spi.py index 997119c..44d07c2 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -2,6 +2,7 @@ ## This file is part of the sigrok project. ## ## Copyright (C) 2011 Gareth McMullin +## Copyright (C) 2012 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,100 +18,94 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -class Sample(): - def __init__(self, data): - self.data = data - def probe(self, probe): - s = ord(self.data[probe / 8]) & (1 << (probe % 8)) - return True if s else False - -def sampleiter(data, unitsize): - for i in range(0, len(data), unitsize): - yield(Sample(data[i:i+unitsize])) - -class Decoder(): - name = 'SPI Decoder' + +import sigrokdecode as srd + +# Annotation formats +ANN_HEX = 0 + +class Decoder(srd.Decoder): + id = 'spi' + name = 'SPI' + longname = 'Serial Peripheral Interface (SPI) bus' desc = '...desc...' - longname = '...longname...' longdesc = '...longdesc...' author = 'Gareth McMullin' email = 'gareth@blacksphere.co.nz' license = 'gplv2+' inputs = ['logic'] outputs = ['spi'] - # Probe names with a set of defaults - probes = {'sdata':0, 'sck':1} + probes = [ + {'id': 'mosi', 'name': 'MOSI', + 'desc': 'SPI MOSI line (Master out, slave in)'}, + {'id': 'miso', 'name': 'MISO', + 'desc': 'SPI MISO line (Master in, slave out)'}, + {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, + ] options = {} + annotations = [ + ['Hex', 'SPI data bytes in hex format'], + ] - def __init__(self, unitsize, **kwargs): - # Metadata comes in here, we don't care for now - #print kwargs - self.unitsize = unitsize - - self.probes = Decoder.probes - self.oldsck = True - self.rxcount = 0 - self.rxdata = 0 + def __init__(self): + self.oldsck = 1 + self.bitcount = 0 + self.mosidata = 0 + self.misodata = 0 self.bytesreceived = 0 + self.samplenum = -1 + + def start(self, metadata): + self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') + self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') def report(self): - return "SPI: %d bytes received" % self.bytesreceived + return 'SPI: %d bytes received' % self.bytesreceived + + def decode(self, ss, es, data): + # HACK! At the moment the number of probes is not handled correctly. + # E.g. if an input file (-i foo.sr) has more than two probes enabled. + # for (samplenum, (mosi, sck, x, y, z, a)) in data: + # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: + for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: - def decode(self, data): - # We should accept a list of samples and iterate... - for sample in sampleiter(data["data"], self.unitsize): + self.samplenum += 1 # FIXME - sck = sample.probe(self.probes["sck"]) - # Sample SDATA on rising SCK + # Sample data on rising SCK edges. if sck == self.oldsck: continue self.oldsck = sck - if not sck: - continue - - # If this is first bit, save timestamp - if self.rxcount == 0: - self.time = data["time"] - # Receive bit into our shift register - sdata = sample.probe(self.probes["sdata"]) - if sdata: - self.rxdata |= 1 << (7 - self.rxcount) - self.rxcount += 1 - # Continue to receive if not a byte yet - if self.rxcount != 8: + if sck == 0: continue - # Received a byte, pass up to sigrok - outdata = {"time":self.time, - "duration":data["time"] + data["duration"] - self.time, - "data":self.rxdata, - "display":("%02X" % self.rxdata), - "type":"spi", - } - print outdata - sigrok.put(outdata) - # Reset decoder state - self.rxdata = 0 - self.rxcount = 0 - # Keep stats for summary - self.bytesreceived += 1 - -if __name__ == "__main__": - data = open("spi_dump.bin").read() - # dummy class to keep Decoder happy for test - class Sigrok(): - def put(self, data): - print "\t", data - sigrok = Sigrok() + # If this is the first bit, save its sample number. + if self.bitcount == 0: + self.start_sample = samplenum + + # Receive bit into our shift register. + if mosi == 1: + self.mosidata |= 1 << (7 - self.bitcount) + if miso == 1: + self.misodata |= 1 << (7 - self.bitcount) - dec = Decoder(driver='ols', unitsize=1, starttime=0) - dec.decode({"time":0, "duration":len(data), "data":data, "type":"logic"}) + self.bitcount += 1 - print dec.summary() -else: - import sigrok + # Continue to receive if not a byte yet. + if self.bitcount != 8: + continue -#Tested with: -# sigrok-cli -d 0:samplerate=1000000:rle=on --time=1s -p 1,2 -a spidec + self.put(self.start_sample, self.samplenum, self.out_proto, + ['data', self.mosidata, self.misodata]) + self.put(self.start_sample, self.samplenum, self.out_ann, + [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, + self.misodata)]]) + # Reset decoder state. + self.mosidata = 0 + self.misodata = 0 + self.bitcount = 0 + + # Keep stats for summary. + self.bytesreceived += 1