X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi.py;h=44d07c260f64bf19d057dc2fac42533d42e91d2d;hb=9b4d8a5753db586648abfe7897c29ad5d5bc77a5;hp=6b5df8092fad5c566f3f19892468ba2d715dcc28;hpb=b1bb5eed4ad056f760bec83e784699dabbd72a18;p=libsigrokdecode.git diff --git a/decoders/spi.py b/decoders/spi.py index 6b5df80..44d07c2 100644 --- a/decoders/spi.py +++ b/decoders/spi.py @@ -2,6 +2,7 @@ ## This file is part of the sigrok project. ## ## Copyright (C) 2011 Gareth McMullin +## Copyright (C) 2012 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -20,6 +21,9 @@ import sigrokdecode as srd +# Annotation formats +ANN_HEX = 0 + class Decoder(srd.Decoder): id = 'spi' name = 'SPI' @@ -32,22 +36,28 @@ class Decoder(srd.Decoder): inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'}, + {'id': 'mosi', 'name': 'MOSI', + 'desc': 'SPI MOSI line (Master out, slave in)'}, + {'id': 'miso', 'name': 'MISO', + 'desc': 'SPI MISO line (Master in, slave out)'}, {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, + {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, ] options = {} annotations = [ - ['TODO', 'TODO'], + ['Hex', 'SPI data bytes in hex format'], ] def __init__(self): self.oldsck = 1 - self.rxcount = 0 - self.rxdata = 0 + self.bitcount = 0 + self.mosidata = 0 + self.misodata = 0 self.bytesreceived = 0 + self.samplenum = -1 def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') + self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') def report(self): @@ -56,37 +66,45 @@ class Decoder(srd.Decoder): def decode(self, ss, es, data): # HACK! At the moment the number of probes is not handled correctly. # E.g. if an input file (-i foo.sr) has more than two probes enabled. - # for (samplenum, (sdata, sck, x, y, z, a)) in data: + # for (samplenum, (mosi, sck, x, y, z, a)) in data: # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: - for (samplenum, (cs, miso, sck, sdata, wp, hold)) in data: + for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: + + self.samplenum += 1 # FIXME - # Sample SDATA on rising SCK. + # Sample data on rising SCK edges. if sck == self.oldsck: continue self.oldsck = sck if sck == 0: continue - # If this is the first bit, save timestamp. - if self.rxcount == 0: - self.time = samplenum + # If this is the first bit, save its sample number. + if self.bitcount == 0: + self.start_sample = samplenum # Receive bit into our shift register. - if sdata == 1: - self.rxdata |= 1 << (7 - self.rxcount) + if mosi == 1: + self.mosidata |= 1 << (7 - self.bitcount) + if miso == 1: + self.misodata |= 1 << (7 - self.bitcount) - self.rxcount += 1 + self.bitcount += 1 # Continue to receive if not a byte yet. - if self.rxcount != 8: + if self.bitcount != 8: continue - # self.put(0, 0, self.out_proto, out_proto) # TODO - self.put(0, 0, self.out_ann, [0, ['0x%02x' % self.rxdata]]) + self.put(self.start_sample, self.samplenum, self.out_proto, + ['data', self.mosidata, self.misodata]) + self.put(self.start_sample, self.samplenum, self.out_ann, + [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, + self.misodata)]]) # Reset decoder state. - self.rxdata = 0 - self.rxcount = 0 + self.mosidata = 0 + self.misodata = 0 + self.bitcount = 0 # Keep stats for summary. self.bytesreceived += 1