X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi.py;h=44d07c260f64bf19d057dc2fac42533d42e91d2d;hb=9b4d8a5753db586648abfe7897c29ad5d5bc77a5;hp=5489319fea87caa22b1fbc7399e9bd8e7ea9700e;hpb=fb53ee5e242be7781b0d34a7d006c630095bcb72;p=libsigrokdecode.git

diff --git a/decoders/spi.py b/decoders/spi.py
index 5489319..44d07c2 100644
--- a/decoders/spi.py
+++ b/decoders/spi.py
@@ -2,6 +2,7 @@
 ## This file is part of the sigrok project.
 ##
 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,86 +19,93 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-import sigrok
+import sigrokdecode as srd
 
-class Sample():
-    def __init__(self, data):
-        self.data = data
-    def probe(self, probe):
-        s = self.data[int(probe / 8)] & (1 << (probe % 8))
-        return True if s else False
+# Annotation formats
+ANN_HEX = 0
 
-def sampleiter(data, unitsize):
-    for i in range(0, len(data), unitsize):
-        yield(Sample(data[i:i+unitsize]))
-
-class Decoder(sigrok.Decoder):
+class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
-    desc = '...desc...'
     longname = 'Serial Peripheral Interface (SPI) bus'
+    desc = '...desc...'
     longdesc = '...longdesc...'
     author = 'Gareth McMullin'
     email = 'gareth@blacksphere.co.nz'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
-    # Probe names with a set of defaults
-    probes = {'sdata':0, 'sck':1}
+    probes = [
+        {'id': 'mosi', 'name': 'MOSI',
+         'desc': 'SPI MOSI line (Master out, slave in)'},
+        {'id': 'miso', 'name': 'MISO',
+         'desc': 'SPI MISO line (Master in, slave out)'},
+        {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
+    ]
     options = {}
+    annotations = [
+        ['Hex', 'SPI data bytes in hex format'],
+    ]
 
     def __init__(self):
-        self.probes = Decoder.probes.copy()
-        self.oldsck = True
-        self.rxcount = 0
-        self.rxdata = 0
+        self.oldsck = 1
+        self.bitcount = 0
+        self.mosidata = 0
+        self.misodata = 0
         self.bytesreceived = 0
-        self.output_protocol = None
-        self.output_annotation = None
+        self.samplenum = -1
 
     def start(self, metadata):
-        self.unitsize = metadata['unitsize']
-        # self.output_protocol = self.output_new(2)
-        self.output_annotation = self.output_new(1)
+        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
+        self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
 
     def report(self):
         return 'SPI: %d bytes received' % self.bytesreceived
 
-    def decode(self, timeoffset, duration, data):
-        # We should accept a list of samples and iterate...
-        for sample in sampleiter(data, self.unitsize):
+    def decode(self, ss, es, data):
+        # HACK! At the moment the number of probes is not handled correctly.
+        # E.g. if an input file (-i foo.sr) has more than two probes enabled.
+        # for (samplenum, (mosi, sck, x, y, z, a)) in data:
+        # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+        for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
 
-            sck = sample.probe(self.probes['sck'])
-            # Sample SDATA on rising SCK
+            self.samplenum += 1 # FIXME
+
+            # Sample data on rising SCK edges.
             if sck == self.oldsck:
                 continue
             self.oldsck = sck
-            if not sck:
+            if sck == 0:
                 continue
 
-            # If this is first bit, save timestamp
-            if self.rxcount == 0:
-                self.time = timeoffset # FIXME
-            # Receive bit into our shift register
-            sdata = sample.probe(self.probes['sdata'])
-            if sdata:
-                self.rxdata |= 1 << (7 - self.rxcount)
-            self.rxcount += 1
-            # Continue to receive if not a byte yet
-            if self.rxcount != 8:
+            # If this is the first bit, save its sample number.
+            if self.bitcount == 0:
+                self.start_sample = samplenum
+
+            # Receive bit into our shift register.
+            if mosi == 1:
+                self.mosidata |= 1 << (7 - self.bitcount)
+            if miso == 1:
+                self.misodata |= 1 << (7 - self.bitcount)
+
+            self.bitcount += 1
+
+            # Continue to receive if not a byte yet.
+            if self.bitcount != 8:
                 continue
-            # Received a byte, pass up to sigrok
-            outdata = {'time':self.time,
-                'duration':timeoffset + duration - self.time,
-                'data':self.rxdata,
-                'display':('%02X' % self.rxdata),
-                'type':'spi',
-            }
-            # self.put(self.output_protocol, 0, 0, out_proto)
-            self.put(self.output_annotation, 0, 0, outdata)
-            # Reset decoder state
-            self.rxdata = 0
-            self.rxcount = 0
-            # Keep stats for summary
+
+            self.put(self.start_sample, self.samplenum, self.out_proto,
+                     ['data', self.mosidata, self.misodata])
+            self.put(self.start_sample, self.samplenum, self.out_ann,
+                     [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
+                     self.misodata)]])
+
+            # Reset decoder state.
+            self.mosidata = 0
+            self.misodata = 0
+            self.bitcount = 0
+
+            # Keep stats for summary.
             self.bytesreceived += 1