X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=9beb4e63b2642358b7447881e22a2fe0376208ed;hb=88567e4abe73a49acf9527aedeed42ee738c7976;hp=4c5aa05e6a7782b0cf934f203dafb6d9b5637292;hpb=4539e9ca58966ce3c9cad4801b16c315e86ace01;p=libsigrokdecode.git diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py index 4c5aa05..9beb4e6 100644 --- a/decoders/spi/pd.py +++ b/decoders/spi/pd.py @@ -70,14 +70,11 @@ spi_mode = { (1, 1): 3, # Mode 3 } -class SamplerateError(Exception): - pass - class ChannelError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'spi' name = 'SPI' longname = 'Serial Peripheral Interface' @@ -124,8 +121,10 @@ class Decoder(srd.Decoder): ) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None - self.oldclk = 1 self.bitcount = 0 self.misodata = self.mosidata = 0 self.misobits = [] @@ -136,10 +135,7 @@ class Decoder(srd.Decoder): self.samplenum = -1 self.ss_transfer = -1 self.cs_was_deasserted = False - self.oldcs = None - self.oldpins = None self.have_cs = self.have_miso = self.have_mosi = None - self.no_cs_notification = False def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: @@ -149,8 +145,9 @@ class Decoder(srd.Decoder): self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_ann = self.register(srd.OUTPUT_ANN) self.out_binary = self.register(srd.OUTPUT_BINARY) - self.out_bitrate = self.register(srd.OUTPUT_META, - meta=(int, 'Bitrate', 'Bitrate during transfers')) + if self.samplerate: + self.out_bitrate = self.register(srd.OUTPUT_META, + meta=(int, 'Bitrate', 'Bitrate during transfers')) self.bw = (self.options['wordsize'] + 7) // 8 def putw(self, data): @@ -213,17 +210,18 @@ class Decoder(srd.Decoder): not self.cs_asserted(cs) if self.have_cs else False ws = self.options['wordsize'] + bo = self.options['bitorder'] # Receive MISO bit into our shift register. if self.have_miso: - if self.options['bitorder'] == 'msb-first': + if bo == 'msb-first': self.misodata |= miso << (ws - 1 - self.bitcount) else: self.misodata |= miso << self.bitcount # Receive MOSI bit into our shift register. if self.have_mosi: - if self.options['bitorder'] == 'msb-first': + if bo == 'msb-first': self.mosidata |= mosi << (ws - 1 - self.bitcount) else: self.mosidata |= mosi << self.bitcount @@ -255,22 +253,23 @@ class Decoder(srd.Decoder): self.putdata() # Meta bitrate. - elapsed = 1 / float(self.samplerate) - elapsed *= (self.samplenum - self.ss_block + 1) - bitrate = int(1 / elapsed * self.options['wordsize']) - self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) + if self.samplerate: + elapsed = 1 / float(self.samplerate) + elapsed *= (self.samplenum - self.ss_block + 1) + bitrate = int(1 / elapsed * ws) + self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) if self.have_cs and self.cs_was_deasserted: self.putw([4, ['CS# was deasserted during this data word!']]) self.reset_decoder_state() - def find_clk_edge(self, miso, mosi, clk, cs): - if self.have_cs and self.oldcs != cs: + def find_clk_edge(self, miso, mosi, clk, cs, first): + if self.have_cs and (first or self.matched[self.have_cs]): # Send all CS# pin value changes. + oldcs = None if first else 1 - cs self.put(self.samplenum, self.samplenum, self.out_python, - ['CS-CHANGE', self.oldcs, cs]) - self.oldcs = cs + ['CS-CHANGE', oldcs, cs]) if self.cs_asserted(cs): self.ss_transfer = self.samplenum @@ -288,11 +287,9 @@ class Decoder(srd.Decoder): return # Ignore sample if the clock pin hasn't changed. - if clk == self.oldclk: + if first or not self.matched[0]: return - self.oldclk = clk - # Sample data on rising/falling clock edge (depends on mode). mode = spi_mode[self.options['cpol'], self.options['cpha']] if mode == 0 and clk == 0: # Sample on rising clock edge @@ -307,27 +304,35 @@ class Decoder(srd.Decoder): # Found the correct clock edge, now get the SPI bit(s). self.handle_bit(miso, mosi, clk, cs) - def decode(self, ss, es, data): - if not self.samplerate: - raise SamplerateError('Cannot decode without samplerate.') - # Either MISO or MOSI can be omitted (but not both). CS# is optional. - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (clk, miso, mosi, cs) = pins, pins - self.have_miso = (miso in (0, 1)) - self.have_mosi = (mosi in (0, 1)) - self.have_cs = (cs in (0, 1)) - - # Either MISO or MOSI (but not both) can be omitted. - if not (self.have_miso or self.have_mosi): - raise ChannelError('Either MISO or MOSI (or both) pins required.') - - # Tell stacked decoders that we don't have a CS# signal. - if not self.no_cs_notification and not self.have_cs: - self.put(0, 0, self.out_python, ['CS-CHANGE', None, None]) - self.no_cs_notification = True - - self.find_clk_edge(miso, mosi, clk, cs) + def decode(self): + # The CLK input is mandatory. Other signals are (individually) + # optional. Yet either MISO or MOSI (or both) must be provided. + # Tell stacked decoders when we don't have a CS# signal. + if not self.has_channel(0): + raise ChannelError('Either MISO or MOSI (or both) pins required.') + self.have_miso = self.has_channel(1) + self.have_mosi = self.has_channel(2) + if not self.have_miso and not self.have_mosi: + raise ChannelError('Either MISO or MOSI (or both) pins required.') + self.have_cs = self.has_channel(3) + if not self.have_cs: + self.put(0, 0, self.out_python, ['CS-CHANGE', None, None]) + + # We want all CLK changes. We want all CS changes if CS is used. + # Map 'have_cs' from boolean to an integer index. This simplifies + # evaluation in other locations. + wait_cond = [{0: 'e'}] + if self.have_cs: + self.have_cs = len(wait_cond) + wait_cond.append({3: 'e'}) + + # "Pixel compatibility" with the v2 implementation. Grab and + # process the very first sample before checking for edges. The + # previous implementation did this by seeding old values with + # None, which led to an immediate "change" in comparison. + (clk, miso, mosi, cs) = self.wait({}) + self.find_clk_edge(miso, mosi, clk, cs, True) + + while True: + (clk, miso, mosi, cs) = self.wait(wait_cond) + self.find_clk_edge(miso, mosi, clk, cs, False)