X-Git-Url: https://sigrok.org/gitweb/?a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=4c5aa05e6a7782b0cf934f203dafb6d9b5637292;hb=fb83ab342944ce8bddfeb87220f311954be8d0a9;hp=25a9f85f9c059b662fefd203f7e364fdd0edfbb2;hpb=1c49e875623918f8893308307f487a1f551daec4;p=libsigrokdecode.git
diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 25a9f85..4c5aa05 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -15,11 +15,13 @@
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see .
##
import sigrokdecode as srd
+from collections import namedtuple
+
+Data = namedtuple('Data', ['ss', 'es', 'val'])
'''
OUTPUT_PYTHON format:
@@ -34,12 +36,16 @@ Packet:
channel was not supplied.
- 'BITS': / contain a list of bit values in this MOSI/MISO data
item, and for each of those also their respective start-/endsample numbers.
- - 'CS CHANGE': is the old CS# pin value, is the new value.
+ - 'CS-CHANGE': is the old CS# pin value, is the new value.
Both data items are Python numbers (0/1), not strings. At the beginning of
- the decoding a packet is generated with = -1 and being the
- initial state of the CS# pin or -1 if the chip select pin is not supplied.
+ the decoding a packet is generated with = None and being the
+ initial state of the CS# pin or None if the chip select pin is not supplied.
+ - 'TRANSFER': / contain a list of Data() namedtuples for each
+ byte transferred during this block of CS# asserted time. Each Data() has
+ fields ss, es, and val.
Examples:
+ ['CS-CHANGE', None, 1]
['CS-CHANGE', 1, 0]
['DATA', 0xff, 0x3a]
['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
@@ -50,6 +56,8 @@ Examples:
['DATA', 0xa8, None]
['DATA', None, 0x55]
['CS-CHANGE', 0, 1]
+ ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...],
+ [Data(ss=80, es=96, val=0x3a), ...]]
'''
# Key: (CPOL, CPHA). Value: SPI mode.
@@ -110,6 +118,10 @@ class Decoder(srd.Decoder):
('mosi-bits', 'MOSI bits', (3,)),
('other', 'Other', (4,)),
)
+ binary = (
+ ('miso', 'MISO'),
+ ('mosi', 'MOSI'),
+ )
def __init__(self):
self.samplerate = None
@@ -118,10 +130,13 @@ class Decoder(srd.Decoder):
self.misodata = self.mosidata = 0
self.misobits = []
self.mosibits = []
+ self.misobytes = []
+ self.mosibytes = []
self.ss_block = -1
self.samplenum = -1
+ self.ss_transfer = -1
self.cs_was_deasserted = False
- self.oldcs = -1
+ self.oldcs = None
self.oldpins = None
self.have_cs = self.have_miso = self.have_mosi = None
self.no_cs_notification = False
@@ -133,8 +148,10 @@ class Decoder(srd.Decoder):
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate during transfers'))
+ self.bw = (self.options['wordsize'] + 7) // 8
def putw(self, data):
self.put(self.ss_block, self.samplenum, self.out_ann, data)
@@ -148,12 +165,21 @@ class Decoder(srd.Decoder):
if self.have_miso:
ss, es = self.misobits[-1][1], self.misobits[0][2]
+ bdata = so.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [0, bdata])
if self.have_mosi:
ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+ bdata = si.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [1, bdata])
self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
self.put(ss, es, self.out_python, ['DATA', si, so])
+ if self.have_miso:
+ self.misobytes.append(Data(ss=ss, es=es, val=so))
+ if self.have_mosi:
+ self.mosibytes.append(Data(ss=ss, es=es, val=si))
+
# Bit annotations.
if self.have_miso:
for bit in self.misobits:
@@ -175,14 +201,16 @@ class Decoder(srd.Decoder):
self.mosibits = [] if self.have_mosi else None
self.bitcount = 0
+ def cs_asserted(self, cs):
+ active_low = (self.options['cs_polarity'] == 'active-low')
+ return (cs == 0) if active_low else (cs == 1)
+
def handle_bit(self, miso, mosi, clk, cs):
# If this is the first bit of a dataword, save its sample number.
if self.bitcount == 0:
self.ss_block = self.samplenum
- self.cs_was_deasserted = False
- if self.have_cs:
- active_low = (self.options['cs_polarity'] == 'active-low')
- self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0)
+ self.cs_was_deasserted = \
+ not self.cs_asserted(cs) if self.have_cs else False
ws = self.options['wordsize']
@@ -243,9 +271,22 @@ class Decoder(srd.Decoder):
self.put(self.samplenum, self.samplenum, self.out_python,
['CS-CHANGE', self.oldcs, cs])
self.oldcs = cs
+
+ if self.cs_asserted(cs):
+ self.ss_transfer = self.samplenum
+ self.misobytes = []
+ self.mosibytes = []
+ else:
+ self.put(self.ss_transfer, self.samplenum, self.out_python,
+ ['TRANSFER', self.mosibytes, self.misobytes])
+
# Reset decoder state when CS# changes (and the CS# pin is used).
self.reset_decoder_state()
+ # We only care about samples if CS# is asserted.
+ if self.have_cs and not self.cs_asserted(cs):
+ return
+
# Ignore sample if the clock pin hasn't changed.
if clk == self.oldclk:
return
@@ -286,7 +327,7 @@ class Decoder(srd.Decoder):
# Tell stacked decoders that we don't have a CS# signal.
if not self.no_cs_notification and not self.have_cs:
- self.put(0, 0, self.out_python, ['CS-CHANGE', -1, -1])
+ self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
self.no_cs_notification = True
self.find_clk_edge(miso, mosi, clk, cs)